Amorphous‐silicon gate‐driver circuits of shared‐node dual pull‐down structure with overlapped output signals

Abstract

Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.

Long Life-Time Amorphous-InGaZnO TFT-Based Shift Register Using a Reset Clock Signal

“…The V th for the TFTs by either AC pulse With the same effective stress time, V th is independent of duty ratio. In other words, the V th of an a-IGZO TFT fabricated on a glass substrate is almost the same under various AC stress conditions [8], [11]. Figure 3 shows the one-stage circuit schematic and timing diagram of the proposed shift register.…”

“…It is well known that low temperature process poly-silicon (LTPS) technology is preferred for shift registers because stable TFTs can be realized by this technology compared to the a-Si technology. However, a-Si TFTs, in spite of their poor bias and temperature stress (BTS) stability [7], recover quickly, making them usable in shift register circuits that are driven by AC signals [8]- [10].…”

New Depletion-Mode IGZO TFT Shift Register

“…In the TFTs of the driving circuit, the low voltage level applied to a gate electrode is equal to that applied to a source (or drain) electrode [12]- [14]. V gs becomes zero under the "off" condition so that it is extremely difficult to turn off 0741-3106/$26.00 © 2010 IEEE the depletion-mode IGZO TFTs in the driving circuit due to considerable drain-source current.…”

“…2(a). It is important that the voltage of a Q-node should be a high level in order to generate an output pulse [13], [14]. However, in the case of a depletionmode IGZO TFT shift register, the voltage of a Q-node could be discharged through T1, T2, and T3 because V gs of these TFTs becomes zero for the period "(2)" as shown in Fig.…”

“…Of the extracted SPICE parameters [15], CGSO (gate-source capacitance) and CGDO (gate-drain capacitance) are 0.45 nF/m. The shift register is operated with a clock frequency of 13.2 kHz by using four-phase overlapped clock signals [13], [14]. The voltages are 20, −5, and −10 V for VGH, VGL, and VGL1, respectively.…”