P‐38: 1Gbps/lane Low Overhead Clock‐Shared Differential Signaling (CSDS) — An Efficient Interface for Large‐Size TFT‐LCDs

Abstract

A clock‐shared differential signaling (CSDS) scheme is newly proposed to support high resolution and large‐Size TFT‐LCDs with less than 3% overheads compared with transmitted data. CSDS adopts single‐level, multi‐dropped differential clocks which is shared among source driver ICs (CDs) and point‐to‐point connection for data lines. The protocol supporting CSDS makes the overhead of data transmission to be less than a few percent, which makes CSDS superior to other interfaces in terms of signal integrity, EMI, simple transmitter, and etc. It also supports flexible CD controls via just changing register values which are delivered by its protocol. And it is proved that CSDS supports 1.1Gbps per lane, which can cover next generation panels such as UD class.

Vertical 3D NAND Flash Memory Technology

“…After our BiCS proposal, several 3D, not simply stacked NAND structures have been proposed. VG-NAND's (Vertical Gate NAND's) were proposed by Samsung and Macronix, which have horizontal poly-silicon TFT NAND string [13]. The issues are the area penalty of select gate portions, and very hard patterning process of control gates and select gates with very thick hard mask, which might be impossible for ultra high density devices.…”

31.4: A 3.4Gbps/lane Low Overhead Clock Embedded Intra‐panel Interface for High Resolution and Large‐Sized TFT‐LCDs

“…They can be categorized into some groups. The first group not uses the clock embedded scheme, in other word, transfer clock and data signals separately, such as CalDriCon, CSDS, PLS, PPDS [5][6][7][8]. This group have simple receiver, but they have skew problem between data and clock signal.…”