P‐53: Study on the Interface Between Passivation and Insulator Layer in TFT with Organic Process

Abstract

This paper introduces a phenomenon named FPC peel off caused by the bad interference between passivation layer and gate insulator layer in TFT contained organic process. We investigated the relationship of this phenomenon with TFT array process and improved the interface characteristics through N2 Plasma and N2 flow skip in passivation deposition step. An optimized VIA hole design was also found which can achieve favourable FPC bonding condition.