In this paper, acryl resin based on ADS process parameters, and its benefit on TFT LCD product is introduced. By analysis of adhesion, exposure energy, developing time, bleach energy and cure parameters, acryl resin optimized process parameters are confirmed. With JSR PC548 positive acryl resin, our ADS product achieves good surface planarization and the product logic power has a nearly 30% decrease.

This paper introduces a phenomenon of the SD bump on the gate layer MoNiTi(bottom)/Cu(top) in GI hole because of the worsening of adhesion between SD layer and gate layer after the copper oxides form on the top copper surface of gate layer. We investigated the relationship of the SD bump with TFT array processes and solved the SD bump issue by reducing the power, gas flow ratio (O2/SF6) or O.E.(%) time of GI etching process. Because these changes of GI etching parameter can decrease the amount and lower the energy of O * and S * free radical in GI etching chamber.

This paper introduces a phenomenon named FPC peel off caused by the bad interference between passivation layer and gate insulator layer in TFT contained organic process. We investigated the relationship of this phenomenon with TFT array process and improved the interface characteristics through N2 Plasma and N2 flow skip in passivation deposition step. An optimized VIA hole design was also found which can achieve favourable FPC bonding condition.