P‐8: Analysis of Degradation Mechanism of Oxide Semiconductor FETs with High Tolerance to Intense NBTIS

Hosaka, Yasuharu; Obonai, Toshimitsu; Dobashi, Masayoshi; Nakayama, Tomohiro; Shima, Yukinori; Ohno, Masakatsu; Yamazaki, Shunpei

doi:10.1002/sdtp.15683

Cited by 4 publications

(2 citation statements)

References 17 publications

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“…The VFET demonstrated remarkable stability, as evidenced by the V th shift measurements taken during tests at 60 C and at gate-source voltages (V gs ) of ±20 V for a duration of 3600 s. Our previous investigations into NBTIS degradation mechanisms have confirmed that FETs incorporating CAAC-OS active layers are less susceptible to NBTIS degradation due to low light absorption coefficients of the OSs and fewer numbers of holes injected into the GI. 25,26 This evidence strongly suggests that the employment of CAAC-OS active layers renders VFETs highly resistant to NBTIS degradation.…”

Section: Evaluation Of Vfet Reliabilitymentioning

confidence: 92%

Vertical field‐effect transistor using c‐axis aligned crystal indium–gallium–zinc oxide on glass substrate and prototype organic light‐emitting diode display

Nakada,

Shima,

Jincho

et al. 2024

J Soc Info Display

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This study developed a technology for a vertical field‐effect transistor (VFET) incorporating c‐axis aligned crystal oxide semiconductor on a Gen 3.5 glass substrate. VFETs, with a channel length of 0.5 μm, demonstrated stable characteristics with minimal variation, higher on‐state current compared with low‐temperature polysilicon FETs, and extremely low off‐state leakage current. A prototype 513‐ppi organic light‐emitting diode display that features a red, green, and blue stripe arrangement and includes an internal compensation circuit with a configuration of six transistors and two capacitors was fabricated by harnessing the advantageous features of VFETs. Such a display was previously unattainable with planar FETs. Thus, the developed VFET technology presents a viable pathway for achieving ultrahigh‐resolution panels on glass substrates.

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Section: Evaluation Of Vfet Reliabilitymentioning

confidence: 92%

Vertical field‐effect transistor using c‐axis aligned crystal indium–gallium–zinc oxide on glass substrate and prototype organic light‐emitting diode display

Nakada,

Shima,

Jincho

et al. 2024

J Soc Info Display

Self Cite

View full text Add to dashboard Cite

show abstract

“…Recently, Hosaka et al reported that cations can diffuse from the active layer into an insulator via the thermal budget, which may hinder our experiments. 31 Therefore, to understand the relationship between the diffusion of cations and variations in V O , we performed a TEM-EDS analysis of the stacked film. Figure 2a shows the cross-sectional TEM images and EDS line scan of the stacked film before and after annealing at 600 °C.…”

Section: Understanding the Impact Of Annealing Temperatures On The Al...mentioning

confidence: 99%

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

Kim

Lee

et al. 2023

ACS Appl. Mater. Interfaces

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Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In0.52Ga0.18Zn0.30O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage (V TH) of 0.05 V, a field-effect mobility of 27.6 cm2/Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a V TH shift of −0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.

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Developing Subthreshold-Swing Limit of PEALD In–Sn–Ga–O Transistor via Atomic-Scaled Sn Control

Lee

Kim

et al. 2022

ACS Appl. Electron. Mater.

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The In−Sn−Ga−O (ITGO) thin-film transistor (TFT) is promising in that it possesses enhanced electrical characteristics and stability because the tin (Sn) has large spherical s orbitals and a high binding energy with oxygen (O). Recently, there have been several reports of ITGO material fabricated via sputtering. Therefore, studies that control Sn composition to achieve unique characteristics and obtain conformal films have been limited. For these reasons, we evaluated plasma-enhanced atomic layer deposition (PEALD)-derived ITGO materials with varied Sn composition. The electrical characteristics are enhanced with the Sn subcycle ratio from 1 to 5 in the ITGO films (carrier concentration: 6.4 × 10 20 to 2.2 × 10 21 cm −3 , resistivity: 8.6 × 10 −4 to 6.1 × 10 −4 Ω cm). These results are due to carrier generation by the Sn, a decrease in oxygen-related defects (22.9% to 19.5%), and suppressed indium-oxide (In 2 O 3 ) crystallinity. To demonstrate their applicability to practical devices, the ITGO films were applied to TFTs as active channel layers. The ITGO TFTs with increasing Sn content show a decrease then increase of subthreshold swing (S.S.) characteristics, while the field-effect mobility (μ FE ) slightly increases. In addition, the ITGO TFTs show improved negative bias illumination stress (NBIS) stability with increasing Sn content, while the turnaround point is observed in the Sn 5 subcycle. As a result, the ITGO TFT with the Sn 3 subcycle shows an extremely low S.S. of 64.8 ± 1.9 mV/decade and an NBIS result of −0.5 V. The outstanding performance of the ITGO TFT with Sn 3 subcycle is attributed to its low number of oxygen-related defects, amorphous structure, and low valence band maximum (VBM) level. Therefore, the ITGO TFTs with optimized Sn content have the advantages of low power consumption and resistance to an environment with illumination.

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P‐8: Analysis of Degradation Mechanism of Oxide Semiconductor FETs with High Tolerance to Intense NBTIS

Cited by 4 publications

References 17 publications

Vertical field‐effect transistor using c‐axis aligned crystal indium–gallium–zinc oxide on glass substrate and prototype organic light‐emitting diode display

Vertical field‐effect transistor using c‐axis aligned crystal indium–gallium–zinc oxide on glass substrate and prototype organic light‐emitting diode display

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

Developing Subthreshold-Swing Limit of PEALD In–Sn–Ga–O Transistor via Atomic-Scaled Sn Control

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