Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility

Abstract

Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In0.52Ga0.18Zn0.30O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage (V TH) of 0.05 V, a field-effect mobility of 27.6 cm2/Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a V TH shift of −0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.

Thermal Dehydrogenation Impact on Positive Bias Stability of Amorphous InSnZnO Thin-Film Transistors

“…These results indicate that the D IT exhibited minimal alteration throughout the PBS and PBTS periods, as shown in Figure g–i. Positive V TH shifts in the transfer curve during PBS and PBTS have previously been documented and elucidated through charge trapping between the channel and gate insulator layers, adsorption of excess oxygen molecules on the backchannel region, and additional defect creation by interstitial oxygen in the bulk channel. ,,,, However, since the bias stress measurements of the fabricated devices were conducted in a vacuum environment, the backchannel effects are likely to be minimized in this case. Additionally, the parallel shift of V TH without significant changes in saturation mobility and SS indicates that the creation of additional defects at shallow levels near the conduction band did not occur under the bias stress conditions.…”

“…Under the 60 °C measurement conditions, there was a tendency for the hysteresis width to increase slightly compared to the 20 °C measurement conditions due to the presence of thermally activated charge trapping. , However, we observed that in both measurement conditions, the slope of the clockwise hysteresis width with respect to the reciprocal stress time significantly decreased with increasing thermal dehydrogenation temperature. In AOS TFTs, the clockwise hysteresis primarily occurs due to the charge trapping caused by interface defects between the gate insulator and the AOS channel. , Therefore, the reduction in the slope of hysteresis width suggests the improvement of the interface quality between the a-ITZO channel and the gate insulator caused by the thermal dehydrogenation process. According to the above analysis data and the electrical characteristic result of a-ITZO TFTs, improving saturation mobility and interface characteristics by decreasing the hydrogen content with thermal dehydrogenation temperature is feasible, as illustrated in Figure .…”

Field Induced Off‐State Instability in InGaZnO Thin‐Film Transistor and its Impact on Synaptic Circuits

“…[35][36][37][38][39][40][41][42][43] A relatively low SBH should be formed in the pristine transistor attributed to the high density of charged states, and possibly charged oxygen vacancy (V 2+ O ) states. [44][45][46] With the application of the off-state bias stress, the electric field toward the gate electrode direction induces electron trapping to V 2+ O at the interface, and the transition occurs from ionized V 2+ O to neutralized V O [47] (Figure 3b). As a result of the occupation of the charged states, the shielding effect is gradually reduced and the barrier is pinned to a higher energy level, increasing the SBH which results in higher contact resistance (Figures S3-S5 and Table S1, Supporting Information).…”

Highly Robust Atomic Layer Deposition‐Indium Gallium Zinc Oxide Thin‐Film Transistors with Hybrid Gate Insulator Fabricated via Two‐Step Atomic Layer Process for High‐Density Integrated All‐Oxide Vertical Complementary Metal‐Oxide‐Semiconductor Applications

“…However, in some cases, devices with excess H and O species in the GI may exhibit negative V TH shifts in the PBTS environment. [42,[50][51][52] To understand the origins of the V TH shifts, we compared the amounts of H and O species obtained via SIMS analysis of Al 2 O 3 deposited using PE-ALD and T-ALD, as shown in Figure S2, Supporting Information. Figure 6b and thermal energy in PBTS environments.…”