p-SiGe nanosheet line tunnel field-effect transistors with ample exploitation of ferroelectric

Thoti, Narasimhulu; Li, Yiming

doi:10.35848/1347-4065/abf13e

Cited by 7 publications

(5 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…15 Specifically, the band-to-band tunneling (BTBT) model of dynamic nonlocal tunneling and trapassisted-tunneling (TAT) model of Hurkx's are utilized for effective evaluations of on-and off-state performances. Landau-Khalatnikov (L-K) as a ferroelectric model is utilized with the predefined Hf 0.5 Zr 0.5 O 2 properties (P and E c is of 10 μC cm −2 and 1MV/cm, respectively 6,9 ). The detailed tunneling model calibrations for Si/Si 0.6 Ge 0.4 materials can be found in our recent articles.…”

Section: Modelling Of Ncvtfetmentioning

confidence: 99%

“…6 Moreover, the HfO 2 (gate-oxide) and HZO (ferroelectric) thickness are carefully selected to have less effect of the oxide-breakdown concerned to the growth and processing. 7 Though several options of utilizing the ferroelectricity are existing, 8,9 here we utilize the universal option of metal-ferroelectric-insulator-semiconductor (MFIS). By utilizing the prominent choices of ferroelectric, the point and vertical TFETs (VTFETs) have been explored as NC-TFETs and NC-VTFETs with experimental and modelling approaches.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

Thoti

2021

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

Ferroelectric materials are promising resources for boosting the performance of line or vertical tunneling-field transistors (VTFETs) by diminishing the voltage requirements. Here, we propose a promising VTFET design which has the benefits of HZO thin films having 50% of Zr composition on Hafnium oxide as Hf 0.5 Zr 0.5 O 2 . The significance of negative capacitance (NC) from Hf 0.5 Zr 0.5 O 2 on to VTFET is explored with the physical factors of the electric field and band-to-band tunneling. In addition, the significant factor of the internal-voltage due to NC is modeled using the metal-ferroelectric-insulator approach. The device on-and off-state currents are optimized with the key factor of vertical tunneling called overlapped source and drain regions for NCVTFET. Using an enhanced vertical tunneling area, hetero-structure (Si/SiGe), and ferroelectric options provides two-time improvement in I on by utilizing the ferroelectric rather than the nominal (without ferroelectric). The device also delivers 40-145 GHz of frequency with low orders (<1.0 fF) of gate-capacitance. The device provides ten-time improvement in I on and two-order reduction in energyefficiency compared to the explored ferroelectric structure.

show abstract

Section: Modelling Of Ncvtfetmentioning

confidence: 99%

mentioning

confidence: 99%

Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

Thoti

2021

ECS J. Solid State Sci. Technol.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Therefore, high operating f needs advanced TFET structures (as stated before). The well identified advanced tunneling options are of through structural (vertical or line-tunneling mechanism based, namely vertical-TFETs [25], area TFETs [12], and so on) and material engineering (direct bandgap semiconductors [26], 2D materials [27], high-κ and ferroelectric as dielectrics [28], and so on) to achieve high current drivability, implies high operating frequency regime. These advanced tunneling boosters are helpful for intrinsic device performance as a conductance booster.…”

Section: Ctfet-inverter Transient Analysesmentioning

confidence: 99%

DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

Thoti,

2023

Nanotechnology

Self Cite

View full text Add to dashboard Cite

In this paper, electrical characteristics of a complementary tunneling field effect transistor (CTFET) is studied computationally for the first time. The design of CTFET is carried with 3D vertically stacked channels (multiple) of n-TFET on top of the p-TFET with gate-all-around (GAA) nanosheet SiGe options. The CTFET technology (using CFETs) is examined for emerging technology nodes as a potential alternative to conventional TFETs. Here, the device level design of CTFET is strictly monitored with DC characteristic behavior under the influence of process variability conditions (traps and temperature). The performance analysis is extended to analyze the capability of CTFET under critical dimensions of vertical pitch (n- to p-TFET separation), where it is identified with high scalability. The results of CTFET-inverter show high- noisemargin (NM) and voltage gains compared to the conventional strained-Si GAATFETs at the supply range (VDD) from 0.7 ≥ VDD ≥ 0.2 V. In addition, the CTFET-inverter circuit performance is analyzed with miller capacitance, power delay product, and intrinsic delay, respectively. With better circuit performance, 12.5% and 21.5% improvements in low and high NMs (NML and NMH) are seen in CTFETs compared to conventional TFETs.

show abstract

“…Thus, it provides more flexibility to tune the vertical tunneling and is easy to use at any device technology node. However, an augmented study is needed for controlled I off , which is discussed in our recent works [29].…”

Section: Design and Working Principle Of Omfs-vtfetmentioning

confidence: 99%

Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

Thoti

2021

Nanotechnology

Self Cite

View full text Add to dashboard Cite

This work illustrates the most effective way of utilizing the ferroelectricity for tunneling field-effect transistors (TFETs). The ferroelectric (Hf0.5Zr0.5O2) in shunt with gate-dielectric is utilized as an optimized metal–ferroelectric–semiconductor (OMFS) option to improve the internal voltage (V int ) for ample utilization of polarization and electric fields of Hf0.5Zr0.5O2 across the tunneling region. The modeling of V int signifies 0.15–1.2 nm reduction in tunneling length (λ) than the nominal metal–ferroelectric–insulator–semiconductor (MFIS) option. Furthermore, the TFET geometry with the scaled-epitaxy region as vertical TFET (VTFET), strained Si0.6Ge0.4 as source, and gate-all-around nanowire options are used as an added advantage for further enhancement of TFET’s performance. As a result, the proposed design (OMFS-VTFET) achieves superior DC and RF performances than the MFIS option of TFET. The figure of merits in terms of DC characteristics in the proposed and optimized structure are of improved on-current (=0.23 mA μm−1), high on-to-off current ratio (=1011), steep subthreshold swing (=33.36 mV dec−1), and superior unity gain cut-off frequency (≥300 GHz). The design is revealed as energy-efficient with significant reduction of energy-efficiency in both logic and memory applications.

show abstract

p-SiGe nanosheet line tunnel field-effect transistors with ample exploitation of ferroelectric

Cited by 7 publications

References 34 publications

Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET

DC and AC characteristics of Si/SiGe based vertically stacked complementary-tunneling FETs

Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

Contact Info

Product

Resources

About