p-Type Conversion of WS₂ and WSe₂ by Position-Selective Oxidation Doping and Its Application in Top Gate Transistors

Abstract

For the complementary operation of two-dimensional (2D) material-based field-effect transistors (FETs), high-performance p-type FETs are essential. In this study, we applied surface charge-transfer doping from WO x , which has a large work function of ∼6.5 eV, selectively to the access region of WS2 and WSe2 by covering the channel region with h-BN. By reducing the Schottky barrier width at the contact and injecting holes into the valence band, the p-type conversion of intrinsically n-type trilayer WSe2 FET was successfully achieved. However, trilayer WS2 did not show clear p-type conversion because its valence band maximum is 0.66 eV lower than that of trilayer WSe2. Although inorganic WO x boasts high air stability and fabrication process compatibility due to its high thermal budget, the trap sites in WO x cause large hysteresis during back gate operation of WSe2 FETs. However, by using top gate (TG) operation with an h-BN protection layer as a TG insulator, a high-performance p-type WSe2 FET with negligible hysteresis was achieved.

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping

“…Our method involves self-aligned TG stacks by van der Waals (vdW) integration, followed by oxygen plasma doping at contact and spacer regions of FETs. Unlike conventional methods, , we demonstrate exceptional electrostatic controllability of 2D p-FETs realized by transferring TG stacks consisting of metal and hBN. The utilization of the self-aligned TG as doping-mask, coupled with subsequent large scale processing compatible oxygen plasma doping, results in a high on/off current ratio of 2.5 × 10 7 , small subthreshold swing ( SS ) of 98 mV dec –1 , and near-zero threshold voltage ( V th ) in WSe 2 p-FETs.…”

“…The detailed process is described in the Supporting Information. Notably, this approach enables simultaneous fabrication of several devices with different gate-lengths, unlike conventional transfer method that requires precise alignment of the transferred dielectric layer and separate metal formed via patterning and deposition processes. , The advantage of our method is further highlighted in following section by the realization of p-FETs with tunable gate-length and the fabrication of PMOS inverters, which were not attainable in previous reports due to the aforementioned limitations. , …”

“…Solid-state surface charge transfer doping (SCTD) using nonstoichiometric oxide has been proposed as a facile hole doping method for achieving high hole doping concentrations in 2D materials. ,− For example, there have been recent reports on a reliable p-type SCTD technique using the oxidized 2D materials, e.g., WSe x O y formed upon oxidation of WSe 2 , from which high hole concentration was induced. , Nonetheless, SCTD applied to 2D materials tends to result in the absence of an off-current state with constantly high on-current, making them unsuitable for use in switching devices. To address this limitation, the lateral junction devices are proposed by patterning the doping profile of the channel area, offering improved electrostatic controllability of oxidized WSe 2 FETs through the generation of a built-in potential. ,,,− Furthermore, using a top-gate (TG) to modulate the built-in potential can be an effective approach for achieving high-performance p-FETs. , However, achieving a narrow top-gate length ( L tg ) in the R&D environment is challenging when using conventional top-gate fabrication methods that employ oxygen plasma doping at the spacer area. Additionally, challenges are presented when 2D materials are employed as a channel, e.g., transfer of dielectric layer and additional lithographic patterning process to precisely positioning TG electrodes, which limit the yield of fabrication process contributing to realization of high-performance p-FETs and p-type metal-oxide-semiconductor (PMOS) inverter …”

“…Next, we performed TG operations on the WSe 2 p-FETs. Figure a represents band structures of the WSe 2 p-FETs fabricated using conventional approach with partially metal covered hBN TG stack following the previous reports. , In this fabrication process, we transferred a 2 μm long hBN and subsequently patterned a 500 nm long TG electrode. The partially metal covered hBN TG stack results in unsatisfactory electrostatic controllability of 2D p-FET, as depicted in Figure b,c.…”

Work Function Modulation of Bi/Au Bilayer System toward p-Type WSe2 FET

“…However, it is widely known to be difficult due to the Fermi level pinning (FLP), in which the Fermi level of typical metals is forcefully fixed close to the conduction band edge. − To achieve high-performance p-type FETs, two strategies can be considered: reducing the SB width and reducing the SB height (SBH). The former can be achieved through surface charge transfer doping using transition metal oxides, which form at the local contact area through oxidation of the 2D channel. , Although this doping method is effective, precise control over the oxidation remains challenging despite the layer-by-layer oxidation manner. Thus, the present study focuses on directly manipulating the SBH by suppressing FLP.…”