PA7200: a PA-RISC processor with integrated high performance MP bus interface

Abstract

A new processor implementing Hewlett-Packard's PA-RISC 1 .I (Precision Architecture) has been designed. This latest design incorporates many improvements over the HP PA7100 CPU including increased frequency, instruction and data cache prefetching, enhanced superscalar execution, and enhanced multiprocessor support. The PA7200 connects directly to a new split transaction, I20 MHz, 64-bit bus capable of supporting multiple processors and multiple outstanding memory reads per processor. A novel fully associative on-chip data cache, which is accessed in parallel with an external data cache, is used to reduce the miss rate and facilitate hardware and software directed prefetching to reduce average memory access time.

Application-adaptive intelligent cache memory system

“…One way to adaptively exploit two types of locality is to design a cache system that consists of two caches having different configurations that are tuned for each type of locality [Gonzalez et al 1995;Milutinovic et al 1996;Kurpanchek et al 1994]. Our previous work has used this strategy, employing a directmapped cache and a fully associative spatial buffer at the same cache level [Lee et al 2000].…”

“…The HP-7200 assist cache [Kurpanchek et al 1994] design places the primary direct-mapped cache in parallel with a small fully associative buffer, guaranteeing single-cycle lookup at both units. Blocks requested from the cache controller, due to a cache miss or a prefetch, are first loaded into the assist buffer, and are only promoted into the direct-mapped cache if they exhibit temporal locality.…”

A Study of the Performance Potential for Dynamic Instruction Hints Selection

“…HP PA-RISC 1.1 architecture [11] defines a 2-bit cache control field, cc, which provides a hint to the processor on how to allocate data in the cache hierarchy. On PA-7200 [16], the processor will not allocate the cache line on the off-chip cache if the cc is specified to indicate poor temporal locality. The cache control field is also included in the prefetch instruction introduced in PA-RISC 2.0 [15].…”

Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors

“…This buffer-similar to a victim cache [23] or the HP PA7200 assist cache [25]-is unlikely to exceed 64 entries. Nonetheless, this is an attractive approach since it does not rely on any information from the processor.…”