PAC DSP Core and Application Processors

Chang, David; Liao, I-Tao; Lee, Jenq-Kuen; Chen, Wenfeng; Tseng, Shau-Yin; Jen, Chein-Wei

doi:10.1109/icme.2006.262455

Cited by 28 publications

(16 citation statements)

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“…The distributed and ping-pong register file organization used in PAC DSP are demonstrated to have 76.8% silicon area and 46.9% access time improvement comparing with its equivalent centralized register files [10]. It was reported that the DSP with such register file organization could achieve comparable performance with state-of-the-art DSPs for popular DSP kernels [4,10], which implies that lower power consumption is expectable due to the much less silicon area. This also reveals the importance of a good code generation strategy.…”

Section: Irregular Register Files and Access Constraintsmentioning

confidence: 99%

“…This article describes a novel register allocation scheme for a clustered VLIW DSP, known as a Parallel Architecture Core (PAC) DSP [3,4,12,13], which is designed with distinctively banked register files in which port access is highly restricted. The PAC DSP employs a heterogeneous design comprising a single scalar unit (for simple arithmetic, address calculation, and program flow control), plus two data-stream processing clusters, each containing a pair of load/store units and ALU/MAC units with powerful SIMD (Single Instruction stream, Multiple Data stream) capabilities; each unit in the clusters can utilize three types of register file, providing different accessing methods and constraints, and the scalar unit has its own accessible register file.…”

Section: Introductionmentioning

confidence: 99%

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PALF: compiler supports for irregular register files in clustered VLIW DSP processors

Lin

You

Lee

2007

Concurrency and Computation

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SUMMARYWide varieties of register file architectures -developed for embedded processorshave turned to aim at reducing the power dissipation and die size these years, by contrast with the traditional unified register file structures. This article presents a novel register allocation scheme for a clustered VLIW DSP, which is designed with distinctively banked register files in which port access is highly restricted. Whilst the organization of the register files is designed to decrease the power consumption by using fewer port connections, the cluster-based design makes register access across clusters an additional issue, and the switched-access nature of the register file demands further investigations into optimizing register assignment for increasing the instruction-level parallelism. We propose a heuristic algorithm, named ping-pong aware local favorable (PALF) register allocation, to obtain advantageous register allocation that is expected to better utilize irregular register file architectures. The results of experiments performed using a compiler based on the Open Research Compiler (ORC), showed significant performance improvement over the original ORC's approach, which is considered to be an optimized approach for common register file architectures.key words: register allocation; ping-pong register file; DSP; VLIW

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Section: Irregular Register Files and Access Constraintsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

PALF: compiler supports for irregular register files in clustered VLIW DSP processors

Lin

You

Lee

2007

Concurrency and Computation

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“…The PAC project [1][2][3] was initiated in 2003 and executed by Industrial Technology Research Institute (ITRI) [4] in Taiwan, of which the target is to provide a fully-programmable solution for next-generation media-rich and multi-function portable devices, such as portable media players and smart phones. The speech, audio, image and video processing on these devices demand extremely high computing power under tight power constraints.…”

Section: Introductionmentioning

confidence: 99%

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

Chang

Lin

et al. 2010

J Sign Process Syst

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In order to develop a low-power and highperformance SoC platform for multimedia applications, the Parallel Architecture Core (PAC) project was initiated in Taiwan in 2003. AVLIW digital signal processor (PACDSP) has been developed from a proprietary instruction set with multimedia-rich instructions, a complexity-effective microarchitecture with an innovative distributed & ping-pong register organization and variable-length VLIW encoding, to a highly-configurable soft IP with several successful silicon implementations. A complete toolchain with an optimizing C compiler has also been developed for PACDSP. A dualcore PAC SoC has been designed and fabricated, which consists of a PACDSP core, an ARM9 core, scratchpad memories, and various on-chip peripherals, to demonstrate the outstanding performance and energy efficiency for multimedia processing such as the real-time H.264 codec. The first part of the two introductory papers of PAC describes the hardware architecture of the PACDSP core, its software development tools, and the PAC SoC with dynamic voltage and frequency scaling (DVFS).

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“…In this paper, we present methods to enable streaming RPC flow to support streaming-function off-loading on asymmetric dual-core architectures, which is applicable to both on PAC [13,14] dual-core platforms and TI OMAP dual-core environments. The concept of streaming RPC provides several advantages.…”

Section: Introductionmentioning

confidence: 99%