Packaging of 11 MPixel CMOS-Integrated SiGe Micro-Mirror Arrays

Abstract

This article reports for the first time on the packaging of 10 cm2 11 MPixel SiGe micro-mirror arrays, intended to be used as spatial light modulator (SLM). Due to very stringent requirements on mounted die flatness (<0.01 mrad), first-level packaging of the SLM die is done using specially designed SiC holders. To avoid trapped particles between die and holder, which would jeopardize the flatness spec, special backside cleaning of the dies (< 1 0.8 tm particle/cm2) is needed before mounting the SLM die on the holder. To enable this backside cleaning and to avoid front-side particles during dicing, handling and wire bonding, a temporary wafer-level or 0-level packaging cap which can be placed and removed at room temperature was developed. Dynamic white light interferometer measurements of packaged dies showed that 99.5°O of 123,648 mirrors tested are within spec.

A Parylene temporary packaging technique for MEMS wafer handling

“…If the MEMS device cannot be tested on a wafer, and a permanent package is not required, temporary wafer level packaging is an interesting alternative. Several temporary packaging methods have been proposed in literature, including thermo-compressive packaging [23], the use of glass caps laminated with UV-sensitive tape [24], or a heat-decomposable bonding ring [25]. These temporary packaging processes involve some challenges, such as the alignment of the capping to the MEMS devices, the debris-free stripping process to decap the package from the devices after the dicing step, etc.…”