Packaging of Copper/Low-k IC Devices: A Novel Direct Fine Pitch Gold Wirebond Ball Interconnects Onto Copper/Low-k Terminal Pads

Chungpaiboonpatana, S.; Shi, Frank G.

doi:10.1109/tadvp.2004.831828

Cited by 22 publications

(3 citation statements)

References 5 publications

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“…Most of planar package researches are focused on the top die surface interconnection and the package layout design. Among the top die surface interconnection methods, the main approaches include, molybdenum buffer layer inter-connection [16], soldering bump implantation over passivation layer [17], embedded direct bonded copper (DBC) structure [18], multi-layer sputtering and curing method [19].…”

Section: A High Temperature Approach Focusing On Developing Power Momentioning

confidence: 99%

Technical approaches towards ultra-high power density SiC inverter in electric vehicle applications

Fan

Ning

et al. 2017

Trans. Electr. Mach. Syst.

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Along with the rapid growth in electric vehicle (EV) market, higher power density and more efficient motor drive inverters are required. It is well known that silicon carbide (SiC) has advantages of high temperature, high efficiency and high switching frequency. It is believed that the appropriate utilization of these merits can pave the way to ultra-high power density inverters. This paper presents issues about SiC chip's current-carrying capability enhancement which is crucial for a compact inverter of tens and hundreds of kilowatts. Technical approaches towards ultra-high power density EV inverter including SiC module packaging, dc-link capacitor function analysis and system level integration are discussed. Different PWM algorithms which may improve efficiency and help to reduce the inverter volume are also studied.

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Section: A High Temperature Approach Focusing On Developing Power Momentioning

confidence: 99%

Technical approaches towards ultra-high power density SiC inverter in electric vehicle applications

Fan

Ning

et al. 2017

Trans. Electr. Mach. Syst.

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“…4. The adhesion strength of interface between the Blok and BD low-k layers is usually weak [7], [11], [14]; thus, the delamination failure along this interface is one important failure mode for Cu/low-k stacks under a mechanical or thermomechanical load, for example, shear and TC tests.…”

Section: B Effect Of Solder Bump Materialsmentioning

confidence: 99%

Reliability Evaluation for Copper/Low-$k$ Structures Based on Experimental and Numerical Methods

Xing

Zhang

Zhu³

et al. 2008

IEEE Trans. Device Mater. Relib.

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Bump shear is widely used to characterize the interfacial strength of Cu/low-k structures. In this paper, the blanket low-k structure was used to evaluate the reliability and strength of Cu/low-k structures based on experiment and finite-element modeling technique. The objectives of this paper are to determine the critical stress parameters for low-k interfaces with different low-k structures, to understand the failure mechanism, and to improve low-k structure reliability by optimizing some parameters. In this paper, a comprehensive parametric study was carried out. Such parameters include the effect of three different low-k structures, high-Pb solder bump versus Pb-free solder bump, different underbump metallization (UBM) thicknesses, barrier-layer material elastic modulus, and shear ram height on low-k structure reliability. The simulation findings can be summarized as follows. The critical stress decreases with the number of layers of low-k structure. An Sn-Ag solder bump results in a higher shear force and stress than a high-Pb solder bump. Reducing the UBM thickness can help improve the low-k structure reliability.

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“…Sawing aggressive Cu/Low-K interconnect with higher metallization scheme has been critical in preventing new reliability failure mode mechanisms that often can be coupled with the inherent package reliability issue and cause conflicting assembly material selection and evaluation of results. 21 The schematic of the bevel first cut structure for double sawing processes is illustrated in Fig. 2.…”

Section: Active Tv Structures and Package Constructionsmentioning

confidence: 99%

Advanced HiCTE flip chip packaging of 90-nm Cu/Low-K chips: Underfill, novel terminal pad structures, and processing optimization

Chungpaiboonpatana

Shi

2005

Journal of Elec Materi

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Packaging of 90-nm Cu/Low-K chips presents a serious challenge, which requires an advanced ceramic flip chip solution. Finer Cu interconnects are expected to interact differently with the current underfill-to-die passivation stack-up structures used for Al or previous Cu technology nodes especially in system level applications. Furthermore, the more porous and brittle-proned advanced Low-K (K Ͻ 3) dielectrics present additional process incompatibility problems such as stress-induced crackings and delaminations. These reliability issues in various stress-relieving passivation structures and materials (i.e., Benzocyclobutene (BCB) and single versus double SiOxNy passivations) have not been extensively studied. This study analyzes the effect of the eight metal layer 90-nm Cu/Low-K flip chip devices through designed experiments using two relatively different underfill materials, standard terminal pad and novel passivation structures, and JEDEC Level-3 reliability stressings: temperature cycling (TC), highly accelerated stress testing (HAST), and high-temperature storage (HTS). Black Diamond Low-K and HiCTE ceramic substrates are employed for the large package form factor. The active Si uses eutectic stencil-pasted SnPb bump and BGA balls with Ti/Ni-V/Al-Cu reflectory thin film-deposited under bump metallurgy (UBM). It is found that the double passivation pad structures are less susceptible to reliability damage for various types of underfills, although a single passivation with BCB coating combined with an optimal underfill can also yield a similar favorable result. The metallurgical effect of delamination cracking, HiCTE flip chip and stress-relieving passivation structures, and the underfill interface failure mode mechanism are examined by functional testing, chemical deprocessings, scanning acoustic microscope (SAM), and scanning electron microscope (SEM)/energy-dispersive x-ray (EDX). The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/Low-K generations.

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Packaging of Copper/Low-k IC Devices: A Novel Direct Fine Pitch Gold Wirebond Ball Interconnects Onto Copper/Low-k Terminal Pads

Cited by 22 publications

References 5 publications

Technical approaches towards ultra-high power density SiC inverter in electric vehicle applications

Technical approaches towards ultra-high power density SiC inverter in electric vehicle applications

Reliability Evaluation for Copper/Low-$k$ Structures Based on Experimental and Numerical Methods

Advanced HiCTE flip chip packaging of 90-nm Cu/Low-K chips: Underfill, novel terminal pad structures, and processing optimization

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