Reliability Evaluation for Copper/Low-$k$ Structures Based on Experimental and Numerical Methods

Xing, Fa; Zhang, Xiaowu; Zhu, W.H.; Chai, Tai Chong

doi:10.1109/tdmr.2008.2002345

Cited by 8 publications

(5 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…They developed the FEM to predict the EM voids, in which three mechanisms including EM, thermo-migration(TM) and stress migration(SM) were considered [22].…”

Section: Trend Of Interconnect Modelingmentioning

confidence: 99%

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Lin¹,

Wu²,

Jia³

2018

View full text Add to dashboard Cite

Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect reliability, a comprehensive review of the published literatures is carried out. This can depict the global trend of ICs' interconnect reliability and help the new entrants to understand the present situation of this area.

show abstract

“…They developed the FEM to predict the EM voids, in which three mechanisms including EM, thermo-migration(TM) and stress migration(SM) were considered [22].…”

Section: Trend Of Interconnect Modelingmentioning

confidence: 99%

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Lin¹,

Wu²,

Jia³

2018

View full text Add to dashboard Cite

show abstract

“…Previous studies have indicated that stress and the corresponding inelastic strains are localized at the edge of the solder/pad interface leading to crack initiation and fracture of the interconnection [3][4][5][6]. The location of stress concentration at the edge of the solder/IMC interface plane during solder ball shear push test is illustrated in Fig.…”

Section: B Stress Evolution During Solder Ball Shear Push Testmentioning

confidence: 99%

“…In this respect, numerous numerical models based on finite element (FE) method have been developed and examined [1][2][3][4][5][6][7][8][9][10][11][12]. The accuracy of FE models is largely dependent on the accuracy of the input model geometry, correct loading and boundary conditions prescribed, and physically sound constitutive equations employed for the package materials being modeled.…”

Section: Introductionmentioning

confidence: 99%

Damage mechanics of solder/IMC interface fracture in Pb-free solder interconnects

Lai

Keat

Tamin

2009

2009 11th Electronics Packaging Technology Conference

View full text Add to dashboard Cite

This study addresses the mechanics of the relatively brittle solder/intermetallic (IMC) interface fracture process using damage mechanics concept. The damage state, ϕ of a material point in the solder/IMC interface, is expressed in terms of orthogonal traction components in a quadratic failure criterion of a cohesive zone model. The model is then employed in a finite element analysis of a solder ball shear push test. The simulated test specimen consists of reflowed SAC405 solderon-OSP copper pad and orthotropic FR4 substrate. Unified inelastic strain constitutive model with optimized material parameters describes the strain rate-response of the SAC405 solder. The cohesive zone model parameter values are compiled from published experimental data on SAC405 solder ball pull tests and shear push tests. The predicted shear tool force-displacement curve compared well with published experimental data. The normal-to-shear traction ratio at the onset of interface fracture is 1.59 indicating significant induced bending effect due to shear tool clearance. Rapid interface crack propagation is predicted following the initiation of crack with the average crack speed up to 24.6 times the applied shear tool speed at 3000 mm/sec. The progressive boundary between damaged (ϕ<1.0) and fractured (ϕ=1.0) interface is interpreted as the interface crack front. The high stress concentration along the edge of the solder/IMC interface facilitates local crack initiation and dictates the shape of the dynamic crack front. IntroductionLead-free solder interconnects have become an integral part of microelectronics chips development due to legislative requirements on environment-friendly devices. The use of SnAg based solders raised the reflow temperature and the upper limit of the reliability temperature cycles. In addition, the use of different surface finishes of the substrate leads to different ball limiting metallurgy in the solder interconnection particularly at the solder/intermetallics (IMC) interface. The mechanics of such solder interconnections under reliability load cycles and device operating conditions dictates the reliability of the assembly.

show abstract

“…The temperature distribution can strongly affect the interconnect resistance, and, consequently, the signal integrity of circuits can be degraded. Furthermore, low-k materials are generally used to reduce the effect on interconnect time delay, crosstalk and dynamic power consumption [8,9]. However, because of the poor thermal conductivity of such materials, most of the *Corresponding author (email: fire5water@hotmail.com) Joule heating produced by the interconnects on every level cannot be transmitted to the heat sink.…”

mentioning

confidence: 99%

Effect of dummy vias on interconnect temperature variation

et al. 2011

View full text Add to dashboard Cite

The number of the dummy via can significantly affect the interconnect average temperature. This paper explores the modeling of the interconnect average temperature in the presence of multiple dummy vias. The proposed model incorporates the multi-via effect into the effective thermal conductivity of the interlayer dielectric (ILD) to obtain accurate results. Using different ILDs, the multi-via effect is analyzed and discussed. Also, the extended applications of the multi-via effect are presented in this paper to obtain the minimum interconnect average temperature increase with a given via separation or number. This study suggests that the multi-via effect should be accounted for in integrated circuits design to optimize the performance and design accuracy of integrated circuits. As feature sizes have decreased, a continuous increase in integration density has resulted in higher overall chip temperature, which makes power dissipation and thermal issues a major impediment in the design of ultra large scale integrated circuits (ULSI) [1][2][3]. Research has shown that on-chip global interconnect self-heating contributes about 34% of the total chip power dissipation in an Intel microprocessor with 130-nm features [4]. Moreover, because of the reduction of the distance between the substrate and the top-most metal layers [5], the substrate temperature variations have an increased effect on interconnect temperature profile. In high-performance integrated circuits (ICs), the peak chip temperature can reach 210°C and the thermal gradients can rise above 50°C when in the GHz frequency regime [6,7]. The temperature distribution can strongly affect the interconnect resistance, and, consequently, the signal integrity of circuits can be degraded. Furthermore, low-k materials are generally used to reduce the effect on interconnect time delay, crosstalk and dynamic power consumption [8,9]. However, because of the poor thermal conductivity of such materials, most of the *Corresponding author (email: fire5water@hotmail.com) Joule heating produced by the interconnects on every level cannot be transmitted to the heat sink. Therefore it accumulates which leads to a larger interconnect temperature rise. However, vias can effectively reduce interconnect temperature increase. Hence the interconnect temperature will not be not as high would be estimated or the previous circumstance [10][11][12][13]. Because of the reasonable thermal conductivity of vias, dummy vias can be introduced to reduce the interconnect temperature in IC design. A dummy via is a kind of via which that used to conduct heat but is not electrically connected [12][13][14][15]. The interconnect temperature profile can be strongly affected by the presence of dummy vias. Over-estimation of the interconnect temperature can lead to design failure or unnecessarily conservative design. Therefore, an accurate prediction of interconnect temperature is a necessary precondition for interconnect characterization.

show abstract

Reliability Evaluation for Copper/Low-$k$ Structures Based on Experimental and Numerical Methods

Cited by 8 publications

References 12 publications

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Damage mechanics of solder/IMC interface fracture in Pb-free solder interconnects

Effect of dummy vias on interconnect temperature variation

Contact Info

Product

Resources

About