The ability to incorporate rigid but high-performance nano-scale non-planar complementary metal-oxide semiconductor (CMOS) electronics with curvilinear, irregular, or asymmetric shapes and surfaces is an arduous but timely challenge in enabling the production of wearable electronics with an in-situ information-processing ability in the digital world. Therefore, we are demonstrating a soft-material enabled double-transfer-based process to integrate flexible, silicon-based, nano-scale, non-planar, fin-shaped field effect transistors (FinFETs) and planar metal-oxide-semiconductor field effect transistors (MOSFETs) on various asymmetric surfaces to study their compatibility and enhanced applicability in various emerging fields. FinFET devices feature sub-20 nm dimensions and state-of-the-art, high-κ/metal gate stacks, showing no performance alteration after the transfer process. A further analysis of the transferred MOSFET devices, featuring 1 µm gate length, exhibits an I ON value of nearly 70 µA/µm (V DS = 2 V, V GS = 2 V) and a low sub-threshold swing of around 90 mV/dec, proving that a soft interfacial material can act both as a strong adhesion/interposing layer between devices and final substrate as well as a means to reduce strain, which ultimately helps maintain the device's performance with insignificant deterioration even at a high bending state. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 5
Results and Discussions:The hetero-integration process is shown in Figure 1. It begins with the release of a thin layer of silicon of about 30 to 35 µm in thickness from a p-type (100) silicon wafer (figure 1a). The procedure of extracting such a fabric consists of deep trench formation followed by isotropic etching-based release, which has been demonstrated with various devices and thicknesses (5-50 µm) by controlling various design parameters, such as the trenches' depth, as explained in detail in our previous works. 25,26 The transfer process is then carried out by placing the released silicon fabric upside-down on a piece of polyimide film (Kapton) or copper foil, which is coated with unbaked photoresist ( Figure 1b). The photoresist layer is meant to protect the topside of the fabric, where electronic devices "sit", and we have found that a thick layer is the most effective (above 2 µm).Once the photoresist is baked, a thin layer of elastomer polydimethylsiloxane (PDMS) is spin coated on top to provide final adhesion and isolation from applied strains ( Figure 1c). The whole stack is then placed on top of the substrate of interest, and the PDMS layer is left for curing (Figure 1d). Finally, the pho...