Packet-based input test data compression techniques

Volkerink, E.; Khoche, A.; Mitra, Subhasish

doi:10.1109/test.2002.1041756

Cited by 64 publications

(30 citation statements)

References 22 publications

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“…For instance, Ichihara et al [20] used statistical codes, Chandra and Chakrabarty [21] made use of Golomb codes, Iyengar et al [22] explored the use of run-length codes, Chandra and Chakrabarty [23] tried frequency-directed run-length codes, and Volkerink et al [24] have investigated the use of Packet-based codes.…”

Section: Related Workmentioning

confidence: 99%

Test data truncation for test quality maximisation under ATE memory depth constraint

Larsson

Edbom

2007

IET Comput. Digit. Tech.

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Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

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Section: Related Workmentioning

confidence: 99%

Test data truncation for test quality maximisation under ATE memory depth constraint

Larsson

Edbom

2007

IET Comput. Digit. Tech.

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“…There are some other techniques which are based on on-chip pattern decompression, such as scan-chain concealment [16], geometric-primitive-based compression [17], mutation encoding [18], deterministic embedded test (reusing the scan chain of one core in a SoC to compress the patterns for another core) [19], packet-based compression [20], and linear feedback shift register (LSFR) reseeding [2], [21], [22].…”

Section: B Test-data Compressionmentioning

confidence: 99%

Nine-coded compression technique for testing embedded cores in SoCs

Tehranipoor

Nourani

Chakrabarty

2005

IEEE Trans. VLSI Syst.

120

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Abstract-This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed-and variable-length blocks. In spite of its simplicity, it provides significant reduction in testdata volume and test-application time. The decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Our technique is flexible and can be efficiently adopted for single-or multiple-scan chain designs. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

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“…Many coding techniques have been proposed for test data compression, which include run-length coding [9], Golomb coding [3], FDR coding [2], EFDR coding [16], statistical coding [10], variablelength index Huffman coding (VIHC) [5] and dictionary coding [14] [25]. Other test data compression techniques such as Illinois scan chain [8], folding counter [7], scan chain concealment(XOR network) [1], mutation encoding [22], Packetbased coding [17] and RESPIN++ [23] were also proposed.…”

Section: Introductionmentioning

confidence: 99%

Combining dictionary coding and LFSR reseeding for test data compression

Sun

Kinney

Vinnakota

2004

Proceedings of the 41st Annual Design Automation Conference

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In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the compression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduces the computation time to find a solution for partial LFSR reseeding. Experimental results on ISCAS89 benchmark circuits show that our approach is better than either dictionary coding or LFSR reseeding, and outperforms several test data compression methods proposed recently.

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Packet-based input test data compression techniques

Abstract: 1 This paper presents a test input data compression

Cited by 64 publications

References 22 publications

Test data truncation for test quality maximisation under ATE memory depth constraint

Test data truncation for test quality maximisation under ATE memory depth constraint

Nine-coded compression technique for testing embedded cores in SoCs

Combining dictionary coding and LFSR reseeding for test data compression

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