Packet Routing in Dynamically Changing Networks on Chip

Majer, Mateusz; Bobda, Christophe; Ahmadinia, Ali; Teich, Jürgen

doi:10.1109/ipdps.2005.323

Cited by 44 publications

(19 citation statements)

References 11 publications

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“…XY routing (two-dimensional order routing) is used for path selection [Hu and Marculescu 2003;Hu et al 2006;Majer et al 2005;Michelogiannakis et al 2007;Ni and McKinley 1993]. It is a low-complexity distributed algorithm without any routing table, and is particularly suitable for mesh or torus-based NoCs.…”

Section: Protocolsmentioning

confidence: 99%

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

et al. 2012

J. Emerg. Technol. Comput. Syst.

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Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. However, in existing optical NoCs, communication locality is poorly supported, and the importance of floorplanning is overlooked. These significantly limit the power efficiency and performance of optical NoCs. In this work, we address these issues and propose a torus-based hierarchical hybrid optical-electronic NoC, called THOE. THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner. It employs several new techniques including floorplan optimization, an adaptive power control mechanism, low-latency control protocols, and hybrid optical-electrical routers with a low-power optical switching fabric. Both of the unfolded and folded torus topologies are explored for THOE. Based on a set of real MPSoC applications, we compared THOE with a typical torus-based optical NoC as well as a torus-based electronic NoC in 45nm on a 256-core MPSoC, using a SystemC-based cycle-accurate NoC simulator. Compared with the matched electronic torus-based NoC, THOE achieves 2.46X performance and 1.51X network switching capacity utilization, with 84% less energy consumption. Compared with the optical torus-based NoC, THOE achieves 4.71X performance and 3.05X network switching capacity utilization, while reducing 99% of energy consumption. Besides real MPSoC applications, a uniform traffic pattern is also used to show the average packet delay and network throughput of THOE. Regarding hardware cost, THOE reduces 75% of laser sources and half of optical receivers compared with the optical torus-based NoC.

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Section: Protocolsmentioning

confidence: 99%

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

et al. 2012

J. Emerg. Technol. Comput. Syst.

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“…NoCs were shown effective in solving the global module interconnect problem [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][21][22][23][24] of such SoCs. One of the primary targets in NoC is a low hardware cost in terms of network area and power [2][3][4][5][6][7][21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

“…One of the primary targets in NoC is a low hardware cost in terms of network area and power [2][3][4][5][6][7][21][22][23][24]. Therefore, most current NoC architectures employ a 2D mesh topology due to the planar nature of VLSI chips, achieving power and area savings [3][4][5][6][7][8][10][11][12][13]23]. In addition, network interface and router logic complexity and power considerations have led to the common use of static, shortest path (SP) routing [3][4][5][6][7]12].…”

Section: Introductionmentioning

confidence: 99%

“…In particular, static routing is cost effective in SoCs where traffic patterns are known a priori and appropriate network topology and capacities can be designed and deployed [3,7]. In other cases, where traffic patterns are not known in advance, NoC routing that performs load balancing based on the dynamic state of the system were proposed [10,13,23,24], requiring more complex routing logic, and possibly network interface that can cope with out-of-order delivery.…”

Section: Introductionmentioning

confidence: 99%

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Routing Table Minimization for Irregular Mesh NoCs

Bolotin¹,

Cidon²,

Ginosar³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unrealistic due to variations in module sizes and shapes, and is not suitable for application-specific NoCs. Consequently, simplistic routing techniques such as XY routing are inadequate, raising the need for low cost alternatives which can work in irregular mesh networks. In this paper we present a novel technique for reducing the total hardware cost of routing tables for both source and distributed routing approaches. The proposed technique is based on applying a fixed routing function combined with minimal deviation tables that are used only when the routing decisions for a given destination deviate from the predefined routing function. We apply this methodology to compare three hardware efficient routing methods for irregular mesh topology NoCs. For each method, we develop path selection algorithms that minimize the overall cost of routing tables. Finally, we demonstrate by simulations on random and specific real application network instances a significant cost saving compared to standard solutions, and examine the scaling of cost savings with growing NoC size.

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“…All these approaches still lack a practical proof of concept because only little research has been spent on dynamically routing signals between dynamically placed modules such as automatic circuit switching (see, e.g., [8]) or dynamic networks on a chip (DyNoC, see, e.g., [9,10,11]). …”

Section: Introductionmentioning

confidence: 99%

Minimizing Communication Cost for Reconfigurable Slot Modules

Fekete

Veen

Majer

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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We discuss the problem of communication-aware module placement in array-like reconfigurable environments, such as the Erlangen Slot Machine (ESM). Bad placement of modules may degrade performance due to increased signal delays and wastes chip space for the reconfigurable multiple bus. We present integer linear programming (ILP) formulations that address both of these problems; both ILPs can be used stand-alone or as building blocks for more involved mathematical models. We validate our models by demonstrating their usefulness for a set of realistic benchmarks.

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Packet Routing in Dynamically Changing Networks on Chip

Cited by 44 publications

References 11 publications

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Routing Table Minimization for Irregular Mesh NoCs

Minimizing Communication Cost for Reconfigurable Slot Modules

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