Packet Transactions

Abstract

Many algorithms for congestion control, scheduling, network measurement, active queue management, and traffic engineering require custom processing of packets in the data plane of a network switch. To run at line rate, these dataplane algorithms must be implemented in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chips. The key challenge is that many data-plane algorithms create and modify algorithmic state. To achieve line-rate programmability for stateful algorithms, we introduce the notion of a packet transaction: a sequential packet-processing code block that is atomic and isolated from other such code blocks.We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated chip-area overhead.

Securing Centralized SDN Control With Distributed Blockchain Technology

“…Their basic idea was to allow the programmer to define stateless flow tables in the switches (like OpenFlow) and also those flow rules that were termed as stateful rules that changed as per the state of a particular flow. Since then, new switch architectures [17,53], stateful data plane platforms [16,48,59], compilers, programming languages, and frameworks [24,25,27,52] have been proposed.…”

In‐network computing—challenges and opportunities

“…Furthermore, these devices run on a time budget principle, limiting the amount of time for packet processing. 13 This is also true for memory, with limits on both access time and number of accesses. This can be avoided by recirculating the packet in the datapath or by sending it to a different device that can process the same function, but will impact latency.…”

P4cep

“…Hence, P4 models the control flow as an imperative program that specifies the execution sequence through the pipeline as a DAG, which rules out loops and thus renders P4 Turing-incomplete. (3) Stateful packet processing on programmable switches has been shown to be challenging [17]. Unsynchronized, concurrent access can lead to inconsistency effects, such as lost updates, which pose a severe threat for the correctness of stateful packet processing algorithms.…”