Packing a modern Xilinx FPGA using RapidSmith

Haroldsen, Travis; Nelson, Brent; Hutchings, Brad

doi:10.1109/reconfig.2016.7857180

Cited by 4 publications

(4 citation statements)

References 10 publications

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“…[10] proposes the AAPACK algorithm, which packs primitives into molecules and assemble clusters from a set of molecules. RSVPACK [11] is a packing algorithm for the XILINX V6 architecture that bridges the gap between academia and industry. DPPACK [12] adopts distributed parallel packing, which shortens the runtime by 1.4-3.2 times with acceptable quality degradation compared to AAPACK.…”

Section: Related Workmentioning

confidence: 99%

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Improving Seed-Based FPGA Packing with Indirect Connection for Realization of Neural Networks

Guo

Tian

et al. 2023

Electronics

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FPGAs are gaining favor among researchers in fields including artificial intelligence and big data due to their configurability and high level of parallelism. As the packing methods indisputably affect the implementation performance of FPGA chips, packing techniques play an important role in the design automation flow of FPGAs. In this paper, we propose a quantitative rule for packing priority of neural network circuits, and optimize the traditional seed-based packing methods with special primitives. The experiment result indicates that the proposed packing method achieves an average decrease of 8.45% in critical path delay compared to the VTR8.0 on Koios deep learning benchmarks.

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Section: Related Workmentioning

confidence: 99%

“…partitioning-based packing [13][14][15][16] effective struggle to handle packing of heterogeneous clusters seed-based packing [6][7][8][9][10][11][12] excel at packing heterogeneous FPGAs the influence of tiles of different sizes on wirelength was ignored…”

Section: Advantages Disadvantagesmentioning

confidence: 99%

Improving Seed-Based FPGA Packing with Indirect Connection for Realization of Neural Networks

Guo

Tian

et al. 2023

Electronics

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“…Once the RM design is imported into RapidSmith2, it is packed using an existing RapidSmith2based packer called RSVPack [37]. This packer targets specifically Xilinx devices and works by repeatedly packing unplaced site clusters with cells.…”

Section: Packing: Rsvpackmentioning

confidence: 99%

“…Once packing completes, Maverick uses RSVPlace [37], also built on top of RapidSmith2, to place the site clusters onto specific sites inside the partial device. It first performs a quick random placement of the site clusters and then executes a simulated annealing placer using a wire-length based cost function.…”

Section: Placement: Rsvplacementioning

confidence: 99%

Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules

Glick

Grigg

Nelson

et al. 2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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Circuit designs for field-programmable gate arrays (FPGAs) are typically compiled by FPGA vendor tools, such as Xilinx's Vivado Design Suite. In recent years, partial reconfiguration (PR) has emerged as a popular technique that allows portions of an FPGA to be dynamically reconfigured after the complete device has been configured with an initial bitstream. However, the nature of current FPGA vendor tools limits further innovation and possible usage models of PR. This thesis presentsMaverick, an open-source proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target PR regions in FPGA designs. Maverick builds upon existing open source tools (Yosys [1], RapidSmith2 [2], and Project X-Ray [3]) to form an end-to-end compilation flow. After an initial static design and PR region are created with Xilinx's Vivado PR flow, Maverick can then compile and configure RMs onto that PR region-without the use of vendor tools. In addition, this work enables users to import and export RMs between Vivado and RapidSmith2.Furthermore, this thesis demonstrates Maverick compiling RMs on both a desktop computer and on the embedded PYNQ-Z1 board, which contains a Zynq 7020 system on chip (SoC). Maverick runs on the ARM processor embedded within the processing system (PS) of the Zynq device, generating partial bitstreams which can then be configured onto a PR region within the programmable logic (PL) fabric of the same Zynq device. This unique case, not possible with current vendor tools like Vivado, demonstrates the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

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Third Party CAD Tools for FPGA Design—A Survey of the Current Landscape

Nelson

2019

Lecture Notes in Computer Science

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Packing a modern Xilinx FPGA using RapidSmith

Cited by 4 publications

References 10 publications

Improving Seed-Based FPGA Packing with Indirect Connection for Realization of Neural Networks

Improving Seed-Based FPGA Packing with Indirect Connection for Realization of Neural Networks

Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules

Third Party CAD Tools for FPGA Design—A Survey of the Current Landscape

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