Pair and swap: An approach to graceful degradation for dependable chip multiprocessors

Abstract

In this paper, we propose a processor-level fault tolerance technique called "Pair and Swap (P&S)" for a multicore chip. In the P&S system, a 2n-cores-CMP (Chip Multiprocessor) which contains 2n processor cores composes n pairs. Two identical copies of a given task are executed on each pair of two processor cores and the results are compared repeatedly. If a fault is detected by a mismatch, partners of the mismatched pair are swapped with another pair and the mismatched task is re-executed from the latest checkpoint. Then, it is decided whether the fault is transient or permanent. If it is permanent, the faulty core is identified and isolated to reconfigure the entire system. P&S enables graceful degradation and tolerates both permanent and transient faults. We evaluate the performance of the proposed P&S and traditional triple module redundancy (TMR) using the Markov chains. The mean computation to failure of the P&S is about 1.4 times larger than that of dynamic TMR scheme.

Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories

“…Recently, several studies have been made on these fault tolerant techniques using CMPs [14][15][16][17][18][19][20]. The goal of this paper is to improve the dependability of NoC-based MPSoCs by extending the Pair and Swap (P&S) methodology [19], [20]. The P&S is a processor-level fault tolerance technique and consists of two phases, the pair phase and the swap phase.…”

An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors

“…In this paper the principle objective is achieved by extending the Pair and Swap (P&S) methodology [4] to include a novel hardware-based decision unit. This unit alleviates the problem of an unreliable component having to provide a comparison result and therefore provides a more consistent level of degradation as the specific piece of hardware is simplistic enough to be considered to have a higher mean time to failure (MTTF) than a complex core.…”

Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories

“…Recently, several studies have been made on these fault tolerant techniques using CMPs [15]- [21]. The goal of this paper is to improve the dependability of NoC-based MPSoCs by extending the Pair and Swap (P&S) methodology [20], [21]. The P&S is a processor-level fault tolerance technique and consists of two phases, the pair phase and the swap phase.…”