Palladium gates for reproducible quantum dots in silicon

Brauns, Matthias; Amitonov, Sergey V.; Spruijtenburg, Paul C.; Zwanenburg, Floris A.

doi:10.1038/s41598-018-24004-y

Cited by 32 publications

(53 citation statements)

References 56 publications

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“…The sample is fabricated on an industrial 300 mm 28 Si wafer substrate. The device consists of a highly resistive n-doped silicon substrate, 1 µm of intrinsic natural silicon, a 100 nm thick 28 Si epilayer with 800 ppm residual 29 Si, covered by 10 nm of thermally grown SiO 2 . We define highly doped n ++ regions by P-ion implantation, activated by an anneal of 30 seconds at 1000 • C in a N 2 atmosphere.…”

Section: A Fabricationmentioning

confidence: 99%

Tunable Coupling and Isolation of Single Electrons in Silicon Metal-Oxide-Semiconductor Quantum Dots

et al. 2019

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Extremely long coherence times, excellent single-qubit gate fidelities, and two-qubit logic have been demonstrated with silicon metal-oxide-semiconductor spin qubits, making it one of the leading platforms for quantum information processing. Despite this, a long-standing challenge in this system has been the demonstration of tunable tunnel coupling between single electrons. Here we overcome this hurdle with gate-defined quantum dots and show couplings that can be tuned on and off for quantum operations. We use charge sensing to discriminate between the (2,0) and (1,1) charge states of a double quantum dot and show excellent charge sensitivity. We demonstrate tunable coupling up to 13 GHz, obtained by fitting charge polarization lines, and tunable tunnel rates down to <1 Hz, deduced from the random telegraph signal. The demonstration of tunable coupling between single electrons in a silicon metal-oxide-semiconductor device provides significant scope for high-fidelity two-qubit logic toward quantum information processing with standard manufacturing.

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Section: A Fabricationmentioning

confidence: 99%

Tunable Coupling and Isolation of Single Electrons in Silicon Metal-Oxide-Semiconductor Quantum Dots

et al. 2019

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“…To achieve small gate pitches and high-density gate structures, multiple layers have to be aligned and electrically insulated [17,18]. Depending on the used material combination, strong variations in gate size and uncontrolled oxidation of the metal gates can lead to additional variations in the final gate structure [62]. Furthermore, multiple gate layers lead to differences in the controllability of the chemical potential depending on the applied voltages due to the different gate dielectric thicknesses above the silicon surface.…”

Section: High-density Spacer Gate Patterningmentioning

confidence: 99%

Spin Qubits Confined to a Silicon Nano-Ridge

et al. 2019

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Electrostatically-defined quantum dots (QDs) in silicon are an attractive platform for quantum computation. Localized single electron spins define qubits and provide excellent manipulation and read-out fidelities. We propose a scalable silicon-based qubit device that can be fabricated by industry-compatible processes. The device consists of a dense array of QDs localized along an etched silicon nano-ridge. Due to its lateral confinement, a simple dense array of metallic top-gates forms an array of QDs with controllable tunnel-couplings. To avoid potential fluctuations because of roughness and charged defects at the nano-ridge sidewall, the cross-section of the nano-ridge is trapezoidal and bounded by atomically-flat {111} facets. In addition to side-gates on top of the low-defect oxidized {111} facets, we implement a global back-gate facilitated by the use of silicon-on-insulator. The most relevant process modules are demonstrated experimentally including anisotropic wet-etching and local oxidation of the silicon nano-ridge, side-gate formation with chemical-mechanical polishing, and top-gate fabrication employing the spacer process. According to electrostatic simulations, our device concept allows forming capacitively-coupled QD double-arrays or adjacent charge detectors for spin-readout. Defining a logical qubit or realizing a single electron conveyor for mid-range qubit-coupling will be future applications.

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“…There are various methods for avoiding unintentional dots in a quantum dot system [10] and reducing strain from room temperature down to < 1 K [11]. Moreover, the modulation of the conduction band due to strain can also be compensated to a limited degree through variation of voltages applied to the gates [12,13].…”

Section: Introductionmentioning

confidence: 99%

Comparison of Strain Effect between Aluminum and Palladium Gated MOS Quantum Dot Systems

2020

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As nano-scale metal-oxide-semiconductor devices are cooled to temperatures below 1 K, detrimental effects due to unintentional dots become apparent. The reproducibility of the location of these unintentional dots suggests that there are other mechanisms in play, such as mechanical strains in the semiconductor introduced by metallic gates. Here, we investigate the formation of strain-induced dots on aluminum and palladium gated metal oxide semiconductor (MOS) quantum devices using COMSOL Multiphysics. Simulation results show that the strain effect on the electrochemical potential of the system can be minimized by replacing aluminum with palladium as the gate material and increasing the thickness of the gate oxide.

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Palladium gates for reproducible quantum dots in silicon

Cited by 32 publications

References 56 publications

Tunable Coupling and Isolation of Single Electrons in Silicon Metal-Oxide-Semiconductor Quantum Dots

Tunable Coupling and Isolation of Single Electrons in Silicon Metal-Oxide-Semiconductor Quantum Dots

Spin Qubits Confined to a Silicon Nano-Ridge

Comparison of Strain Effect between Aluminum and Palladium Gated MOS Quantum Dot Systems

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