PALMED: Throughput Characterization for Superscalar Architectures

Abstract

In a super-scalar architecture, the scheduler dynamically assigns micro-operations (µOPs) to execution ports. The port mapping of an architecture describes how an instruction decomposes into µOPs and lists for each µOP the set of ports it can be mapped to. It is used by compilers and performance debugging tools to characterize the performance throughput of a sequence of instructions repeatedly executed as the core component of a loop.This paper introduces a dual equivalent representation: The resource mapping of an architecture is an abstract model where, to be executed, an instruction must use a set of abstract resources, themselves representing combinations of execution ports. For a given architecture, finding a port mapping is an important but difficult problem. Building a resource mapping is a more tractable problem and provides a simpler and equivalent model. This paper describes Palmed, a tool that automatically builds a resource mapping for pipelined, super-scalar, out-of-order CPU architectures. Palmed does not require hardware performance counters, and relies solely on runtime measurements.We evaluate the pertinence of our dual representation for throughput modeling by extracting a representative set of basic-blocks from the compiled binaries of the SPEC CPU 2017 benchmarks. We compared the throughput predicted by existing machine models to that produced by Palmed, and found comparable accuracy to state-of-the art tools, achieving sub-10 % mean square error rate on this workload on Intel's Skylake microarchitecture.

Explainable Port Mapping Inference with Sparse Performance Counters for AMD's Zen Architectures

“…With a throughput of 6 IPC and up to 4 ports per µop [15, Chapters 23-24], Zen3 and Zen4 could therefore be handled similarly as the previous Zen generations. 7 PMEvo [29] and Palmed [14] as points of comparison in Section 4.5. Since Zen+ does not have full per-port µop counters, the original uops.info algorithm is not applicable.…”

“…We evaluate our Zen+ port mapping quantitatively by comparing its throughput prediction accuracy against PMEvo [29] and Palmed [14]. 9 As port mappings model only the use of functional units, we focus on instruction sequences whose throughput is not limited by data dependencies.…”

“…In contrast to the uops.info algorithm, PMEvo's evolutionary algorithm cannot provide explanatory microbenchmarks to bolster confidence in the results. Palmed [14] infers conjunctive resource mappings with good performance prediction results, but they do not map directly to the microarchitecture and therefore do not fit into existing tools.…”

AnICA: Analyzing Inconsistencies in Microarchitectural Code Analyzers

“…Approaches that infer models for throughput predictors are also evaluated against existing ones on a measured ground truth: PMEvo [Ritter and Hack 2020] and Palmed [Derumigny et al 2022] both use basic blocks without data dependencies, whose throughput is bound by the processor's functional units. For Palmed, the basic blocks mirror basic blocks observed in the binaries of benchmark suites (without the dependencies).…”

“…The AnICA algorithm can also be applied to subcomponents of performance models that affect only individual aspects of basic block throughput prediction. For instance, approaches like uops.info [Abel and Reineke 2019], PMEvo [Ritter and Hack 2020], and Palmed [Derumigny et al 2022] build models for how individual instructions use a CPU's execution resources. These models are able to predict the throughput of basic blocks without data dependencies.…”