[Paper] 4.0 μm Stacked Voltage Mode Global Shutter Pixels with Single Exposure High Dynamic Range and Phase Detection Auto Focus Capability

Miyauchi, Katsuki; Mori, K.; Isozaki, Toshiyuki; Sawai, Yusuke; Yasuda, Naoto; Chien, Hung‐Chang; Fu, Ken; Takayanagi, Isao; Nakamura, Junichi

doi:10.3169/mta.10.234

Cited by 2 publications

(3 citation statements)

References 24 publications

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“…Thus, the SEHDR approach is becoming increasingly attractive. SEHDR is realized with dual conversion gain (DCG) pixels [13][14][15] or lateral overflow integration capacitor (LOFIC) pixels [14][15][16][17][18][19][20][21][22][23], in which the low-conversion-gain (LCG) signal and high-conversion-gain (HCG) signal are combined, as shown in Figure 1b. In DCG pixels, the photoelectrons integrated in a photodiode (PD) are read out twice in different gains, namely LCG and HCG.…”

Section: Introductionmentioning

confidence: 99%

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor

Otani

Ogawa

Miyauchi³

et al. 2023

Sensors

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A lateral overflow integration capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensor can realize high-dynamic-range (HDR) imaging with combination of a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for electron-referred noise floor. However, LOFIC-CMOS image sensor requires a two-channel read-out chain for LCG and HCG signals whose polarities are inverted. In order to provide an area-efficient LOFIC-CMOS image sensor, a one-channel read-out chain that can process both HCG and LCG signals is presented in this paper. An up/down double-sampling circuit composed of an inverting amplifier for HCG signals and a non-inverting attenuator for LCG signals can reduce the area of the read-out chain by half compared to the conventional two-channel read-out chain. A test chip is fabricated in a 0.18 μm CMOS process with a metal–insulator–metal (MIM) capacitor, achieving a readout noise of 130 μVrms for the HCG signal and 1.19 V for the LCG input window. The performance is equivalent to 103 dB of the dynamic range with our previous LOFIC pixel in which HCG and LCG conversion gains are, respectively, 160 μV/e− and 10 μV/e−.

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Section: Introductionmentioning

confidence: 99%

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor

Otani

Ogawa

Miyauchi³

et al. 2023

Sensors

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“…Recently, to achieve over 100 dB dynamic range (DR), a lateral overflow integration capacitor (LOFIC) scheme [1][2][3][4][5][6] and a triple quantization digital pixel sensor [7][8][9] have been developed. To achieve high DR (HDR), a couple of signal readout modes with different pixel gains are implemented in these sensors, and one of the factors to define the performance at the mode transition points, such as the signal-to-noise ratio and linearity, is PDFWC [3].…”

Section: Introductionmentioning

confidence: 99%

“…Although similar models in [13][14][15][16][17] are used in this work, minor modifications are needed for our pixel [7][8][9] because of its unique structure with the buried overflow path under the transfer gate [4][5][6]. Figure 3 shows the PD cross-section and potential of the buried overflow path, which is formed by the low concentration n-layer under TG.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Light Intensity and Charge Holding Time Dependence of Pinned Photodiode Full Well Capacity

Miyauchi,

Isozaki,

Ikeno

et al. 2023

Sensors

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In this paper, the light intensity and charge holding time dependence of pinned photodiode (PD) full well capacity (FWC) are studied for our pixel structure with a buried overflow path under the transfer gate. The formulae for PDFWC derived from a simple analytical model show that the relation between light intensity and PDFWC is logarithmic because PDFWC is determined by the balance between the photo-generated current and overflow current under the bright condition. Furthermore, with using pulsed light before a charge holding operation in PD, the accumulated charges in PD decrease with the holding time due to the overflow current, and finally, it reaches equilibrium PDFWC. The analytical model has been successfully validated by the technology computer-aided design (TCAD) device simulation and actual device measurement.

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[Paper] 4.0 μm Stacked Voltage Mode Global Shutter Pixels with Single Exposure High Dynamic Range and Phase Detection Auto Focus Capability

Cited by 2 publications

References 24 publications

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor

Analysis of Light Intensity and Charge Holding Time Dependence of Pinned Photodiode Full Well Capacity

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