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A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

In this paper, two types of 4.0 µm back side illuminated stacked voltage mode global shutter pixels implemented in a prototype CMOS image sensor are reported. One is a pixel with a lateral overflow integration capacitor (LOFIC) to expand the sensor dynamic range and the other is a pixel having dual photodiodes and dual conversion gains which enables the phase detection auto focus capability with single exposure high dynamic range (SEHDR). Thanks to the LOFIC and the dual conversion gain technologies, SEHDR of 90 dB and 77 dB has been achieved in the global shutter mode.

It is anticipated that ubiquitous computer vision (CV) and artificial intelligence (AI) applications used on mobile devices will grow significantly. Such applications require battery-powered, always-on mobile devices to support indoor/outdoor, day/night usages. A global shutter (GS), stacked digital pixel sensor (DPS) is a promising candidate to meet such requirements because of its potential for ultralow-power, ultrahigh dynamic range (HDR), and a small form factor. This article presents a prototype 4.0-µm stacked DPS operating in its dual quantization (2Q) to realize HDR. The 4.0-µm DPS pixel is formed with two layers, a backside illuminated pinned photodiode (PD) pixel on the top layer and an in-pixel analog-to-digital conversion (ADC) circuit with 9-bit static random access memory (SRAM) on the bottom layer. A Cu-to-Cu hybrid bonding (HB) technology is used to connect the two layers via pixel-level interconnect. In the 2Q scheme, a time-stamp (TS) quantization and a linear ADC are performed sequentially in the same frame, which extends the dynamic range (DR) with a small number of ADC bits of 9. The DPS with a 1024 × 832 pixel array has achieved a single-exposure ultra HDR of 107 dB in a single frame. The nonlinear conversion characteristic of the TS mode provides an equivalent full well capacity (FWC) of 2000ke − , while the noise floor in the linear ADC mode is 8.3e − . Index Terms-CMOS image sensor (CIS), computer vision (CV) sensor, digital pixel sensor (DPS), global shutter (GS), high dynamic range (HDR), noise analysis, stacked process. I. INTRODUCTIONT HE digital pixel sensor (DPS) architecture [1], [2] was studied with high expectation to achieve high-speed, lowpower, and high dynamic range (HDR) [3], [4] in a global shutter (GS) operation in 1990s to early 2000s. However, its Manuscript