Paradigm Shift for NBTI Characterization in Ultra-Scaled CMOS Technologies

Denais, M.; Bravaix, A.; Huard, V.; Parthasarathy, C.; Guérin, C.; Ribes, G.; Perrier, F.; Mairy, M.; Roy, D.

doi:10.1109/relphy.2006.251349

Cited by 27 publications

(11 citation statements)

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“…The BTI effect is usually taken into account by just considering the degradation of the threshold voltage [4]. This is also due to the difficulty of separately extracting multiple components that contribute to BTI degradation, without causing partial recovery of degradation during measurement [5].…”

Section: Aging Modeling For Circuit Simulationmentioning

confidence: 99%

“…Therefore, explicit dependence on V bs has been added. Similarly, for enhanced accuracy in nanometer processes, where the HCI effect increases with temperature [16], Arrhenius dependence on temperature has been included, as in [4].…”

Section: The Hci Modelmentioning

confidence: 99%

“…When a constant bias is applied, the amount of trapped charge increases continuously, further degrading the threshold voltage V TH and decreasing the channel carrier mobility. This effect is also strongly proportional with the device operating temperature [4]. In the case of a variable gate voltage, some of the trapped charges can become de-trapped, which leads to a partial recovery of the degradation, depending on the trap location and trapping/detrapping time constants [2,5].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An accurate MOSFET aging model for 28nm integrated circuit simulation

Tudor

Wang

Chen

et al. 2012

Microelectronics Reliability

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Section: Aging Modeling For Circuit Simulationmentioning

confidence: 99%

Section: The Hci Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An accurate MOSFET aging model for 28nm integrated circuit simulation

Tudor

Wang

Chen

et al. 2012

Microelectronics Reliability

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“…To accurately measure the effects of NBTI, this measurement must be done quickly to avoid the effects of recovery, which has been reported to occur even for measurement windows of a few microseconds [7]. On-the-fly techniques that minimize the recovery effect have been examined in [6], [7], [9], [13], [14], and [16]. Denais et al proposed a measurement technique in which the stress voltage is kept quasi-constant while the linear drain current is measured to monitor device degradation.…”

Section: Previous Reliabiltiy Monitoring Techniquesmentioning

confidence: 99%

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Kim

Persaud

Kim

2008

IEEE J. Solid-State Circuits

203

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Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit design. In this study, we present a fully digital on-chip reliability monitor for high-resolution frequency degradation measurements of digital circuits. The proposed technique measures the beat frequency of two ring oscillators, one stressed and the other unstressed, to achieve 50 higher delay sensing resolution than that of prior techniques. The differential frequency measurement technique also eliminates the effect of common-mode environmental variation such as temperature drifts between each sampling points. A 265 132 m 2 test chip implementing this design has been fabricated in a 1.2 V, 130 nm CMOS technology. The measured resolution of the proposed monitoring circuit was 0.02%, as the ring oscillator in this design has a period of 4 ns; this translates to a temporal resolution of 0.8 ps. The 2 s measurement time was sufficiently short to suppress the unwanted recovery effect from concealing the actual circuit degradation.

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“…Fig.4 successive V tri gers a fresh recovery dynamic even as Idl at the constant factor. The recovery is seen to have an universal behavior r gg y dyn n depending only on the time of stress (tst,ss) and time of recovery previous V, recovers and tends to stabilize (to a "plateau level" (trelax) [12] and is given as:…”

Section: Degradation In Pmosfetsmentioning

confidence: 99%

Reliability of Ultra Thin Gate Oxide CMOS Devices: Design Perspective

Parthasarathy¹,

Denais²,

Huard³

et al.

2006 IEEE International Conference on IC Design and Technology

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channel PMOSFET with constant NBTI level and changing amplitude (and hence changing CHC effect) [8]. In this work, we Assessment of design implications due to degradation of CMOS describe a methodology to be able to view the interaction between devices is increasingly required in the latest technologies. This paper NBTI and CHC as it occurs. discusses degradation due to channel hot carriers, NBTI and oxide breakdown from a design perspective -in terms of characterization, mechanisms and circuit analysis -introducing assessment of Vgs multiple degradation modes on same device.----------

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Paradigm Shift for NBTI Characterization in Ultra-Scaled CMOS Technologies

Cited by 27 publications

References 0 publications

An accurate MOSFET aging model for 28nm integrated circuit simulation

An accurate MOSFET aging model for 28nm integrated circuit simulation

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Reliability of Ultra Thin Gate Oxide CMOS Devices: Design Perspective

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