Parallel AES algorithm for fast Data Encryption on GPU

Le, Deguang; Jin-yi, Chang; Gou, Xingdou; Zhang, Ankang; Lu, Conglan

doi:10.1109/iccet.2010.5486259

Cited by 19 publications

(8 citation statements)

References 8 publications

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“…The exchange of keys between CPU and GPU may be a concern for some applications and should be analyzed very carefully. Power issues were not addressed in Cook et al [2005], Manavski [2007], and Deguang et al [2010], but this point should also be analyzed to evaluate its impact on the global power budget.…”

Section: Crypto Coprocessorsmentioning

confidence: 99%

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Architectures of flexible symmetric key crypto engines—a survey

et al. 2013

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Throughput, flexibility, and security form the design trilogy of reconfigurable crypto engines; they must be carefully considered without reducing the major role of classical design constraints, such as surface, power consumption, dependability, and cost. Applications such as network security, Virtual Private Networks (VPN), Digital Rights Management (DRM), and pay per view have drawn attention to these three constraints. For more than ten years, many studies in the field of cryptographic engineering have focused on the design of optimized high-throughput hardware cryptographic cores (e.g., symmetric and asymmetric key block ciphers, stream ciphers, and hash functions). The flexibility of cryptographic systems plays a very important role in their practical application. Reconfigurable hardware systems can evolve with algorithms, face up to new types of attacks, and guarantee interoperability between countries and institutions. The flexibility of reconfigurable crypto processors and crypto coprocessors has reached new levels with the emergence of dynamically reconfigurable hardware architectures and tools. Last but not least, the security of systems that handle confidential information needs to be thoroughly evaluated at the design stage in order to meet security objectives that depend on the importance of the information to be protected and on the cost of protection. Usually, designers tackle security problems at the same time as other design constraints and in many cases target only one security objective, for example, a side-channel attack countermeasures, fault tolerance capability, or the monitoring of the device environment. Only a few authors have addressed all three design constraints at the same time. In particular, key management security (e.g., secure key generation and transmission, the use of a hierarchical key structure composed of session keys and master keys) has frequently been neglected to the benefit of performance and/or flexibility. Nevertheless, a few authors propose original processor architectures based on multi-crypto-processor structures and reconfigurable cryptographic arrays. In this article, we review published works on symmetric key crypto engines and present current trends and design challenges.

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Section: Crypto Coprocessorsmentioning

confidence: 99%

“…Some interesting works have considered the use of a GPU as a crypto processor combined with a CPU [Cook et al 2005;Manavski 2007;Deguang et al 2010]. Such approaches are motivated by the widespread adoption of GPUs in many embedded systems.…”

Section: Crypto Coprocessorsmentioning

confidence: 99%

Architectures of flexible symmetric key crypto engines—a survey

et al. 2013

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“…et. al., "Parallel AES Algorithm for Fast Data Encryption on GPU", 2010 [4] The researchers proposed a new algorithm for AES parallel encryption based on technologies of GPU parallel computing that designed and implemented a fast data encryption system. The test proves that proposed approach can accelerate the speed of AES encryption significantly.…”

Section: Related Workmentioning

confidence: 99%

An Enhancement Method Based on Modifying CFB Mode for Key Generation in AES Algorithm

Hammod¹,

Al-Rawi²,

Abdulah³

2016

ETJ

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There are two very important characteristics in the block cipher, the amount of time for encryption process and key complexity which caused increasing the complexity of encryption process. This research aims to enhance the key generation of Advanced Encryption Standard (AES) algorithm with high efficiency. The proposed enhancement method architecture based on modifying cipher feedback (MCFB) mode which produce key block from each key generation step in addition to represent current output that is repeated lyre used as input to produce next key block. In the block cipher encryption step, two processes are implemented: Substitution bytes process and Shift rows process. This proposed method improves the performance, efficiency, and speed of the encryption algorithm.

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“…Its importance is further understood by its use in numerous security protocols and systems, including SSL/TLS for internet security, VPNs for secure remote access, and encrypted storage solutions. The strength and versatility of AES make it a cornerstone of data protection in the digital age [14]. As network speeds soar into the gigabits-persecond (Gbps) range, software implementations of cryptographic algorithms struggle to keep pace [15].…”

Section: Introductionmentioning

confidence: 99%

“…In [2], a comparative study shows that the hardware implementation of the AES algorithm is significantly faster when compared to its software implementation. In recent years, many hardware-based implementations have been proposed in literature [11][12][13][14][15][16][17][18][19][20][21][22][23]. Papers [3][4][5], implementing the said algorithm on different FPGA boards, successfully obtaining high throughput as high as around 30Gbps.…”

Section: Introductionmentioning

confidence: 99%

Hardware Accelerated AES: RTL to GDS

Kulkarni

2024

IJSREM

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This paper presents a hardware-accelerated Advanced Encryption Standard (AES) implementation featuring an 11-stage pipelined architecture and an optimized subkey generation scheme for enhanced performance. This design is implemented in Verilog and verified through waveform analysis. Operating at a maximum clock frequency of 100 MHz, our implementation achieves significant efficiency. The final design occupies an area of 1.44 mm2 and consists of 32,424 standard cells, with a power consumption of 32 mW at the typical corner. Furthermore, the entire design flow, from synthesis to layout (GDSII), is achieved using OpenLane, an open-source Electronic Design Automation (EDA) tool. This democratization of hardware design empowers a wider range of participants, particularly students and researchers, to efficiently implement their designs and gain hands-on experience without the constraints of expensive commercial tools. This fosters innovation and accelerates progress by allowing a broader community to contribute to technological advancements. Index Terms—OpenLane, Open-source , EDA, Pipelined AES, RTL to GDSII

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Parallel AES algorithm for fast Data Encryption on GPU

Cited by 19 publications

References 8 publications

Architectures of flexible symmetric key crypto engines—a survey

Architectures of flexible symmetric key crypto engines—a survey

An Enhancement Method Based on Modifying CFB Mode for Key Generation in AES Algorithm

Hardware Accelerated AES: RTL to GDS

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