Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

Yang, Yoon Seok; Bahn, Jun Ho; Lee, Seung Eun; Bagherzadeh, Nader

doi:10.1109/itng.2009.163

Cited by 23 publications

(7 citation statements)

References 14 publications

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“…Various researchers have proposed block cipher algorithms in different parallel implementations, which are based on a hard‐wired circuit and a reconfigurable processor . A block cryptographic LSI, such as an AES application‐specific integration circuit (ASIC), contains the same ten units, which can execute one round of the algorithm.…”

Section: Interleaved‐bitslice Implementation For Parallel Block Ciphementioning

confidence: 99%

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Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Kumaki

Koide

Fujino

2016

IEEJ Transactions Elec Engng

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This paper presents secure data processing with a massive-parallel single-instruction multiple-data (SIMD) matrix for embedded system-on-chip (SoC) in digital-convergence mobile devices. Recent mobile devices are required to use private-informationsecure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end-user's operation for maintaining the safety condition. To satisfy these security-related requirements, we propose the interleaved-bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massiveparallel SIMD matrix processor (MX-1) for interleaved-bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization-approved block ciphers, a data encryption standard (DES), triple-DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX-1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX-1 results are almost constant for all confidentiality modes. The practical-use energy efficiency of parallel block cipher processing with the evaluation board for MX-1 was found to be about 4.8 times higher than that of a BeagleBoard-xM, which is a single-board computer and uses the ARM Cortex-A8 mobile processor. Furthermore, to improve the operation of a single-bit logical function, we propose the development of a multi-bit logical library for interleaved-bitslice cipher processing with MX-1. Thus, the number of clock cycles is the smallest among those reported in other related-studies. Consequently, interleaved-bitslice block cipher processing with five confidentiality modes on MX-1 is effective for the implementation of parallel block cipher processing for several digital-convergence mobile devices.

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Section: Interleaved‐bitslice Implementation For Parallel Block Ciphementioning

confidence: 99%

“…). A parallel and pipeline execution method for the block cipher is implemented on an NoC . This implementation is used for programmable implementation in which the parallelized and pipelined tasks are allocated by the mapping strategy to each PE.…”

Section: Interleaved‐bitslice Implementation For Parallel Block Ciphementioning

confidence: 99%

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Kumaki

Koide

Fujino

2016

IEEJ Transactions Elec Engng

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“…Among the real applications, T264 decoder is a typical video processing application. AES encoder/decoder are typical encryption applications [32] . The automotive and consumer from E3S are used in literatures as [7].…”

Section: Benchmark Characteristicsmentioning

confidence: 99%

“…We follow the task partition in [32] and profile the corresponding tasks in the code of the AES decoder and encoder, which are partitioned into four pipeline stages and duplicated to 16 tasks. The tasks of automotive and consumer from E3S are obtained from MiBench .…”

Section: Benchmark Characteristicsmentioning

confidence: 99%

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Wang

Liu

Yang

et al. 2013

J. Comput. Sci. Technol.

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Abstract3-D Networks-on-Chip (NoC) emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips (MPSoCs). Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging, as the arrival order and task graphs of the target applications are typically not known a priori, which can be further complicated by stringent energy requirements for NoC systems. This paper thus presents an energy-aware run-time incremental mapping algorithm (ERIM) for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores, while reducing the fragmentation effect on the incoming applications to be mapped, and simultaneously satisfying the thermal constraints imposed on each incoming application. Specifically, incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing. Fragment tiles due to system fragmentation can be gleaned for better resource utilization. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM, and the results are compared against the optimal mapping algorithm (branch-and-bound) and two heuristic algorithms (TB and TL). The experiments show that ERIM outperforms TB and TL methods with significant energy saving (more than 10%), much reduced average response time, and improved system utilization.

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“…The compact OpenRISC is connected with our optimised router (Bahn, Lee and Bagherzadeh 2007) through the NI (Lee, Bahn, Yang, and Bagherzadeh 2008). NePA supports programmability and digital signal processing and encryption applications (Bahn et al 2008a,b;Yang, Bahn, Lee and Bagherzadeh 2009) have been implemented and tested to show its potential as an embedded multi-core solution.…”

Section: Introductionmentioning

confidence: 99%

Ray tracing on a networked processor array

Yang

Lee

Chen

et al. 2010

International Journal of Electronics

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As computation costs increase to meet design requirements for computationintensive graphics applications on today's embedded systems, the pressure to develop high-performance parallel processors on a chip will increase. Acceleration of the ray tracing computation has become a major issue as the computer graphics industry demands for rendering realistic images. Network-on-chip (NoC) techniques that interconnect multiple processing elements with routers are the solution for reducing computation time and power consumption by parallel processing on a chip. It is also essential to meet the scalability and complexity challenges for system-on-chip (SoC). In this article, we describe a parallel ray tracing application mapping on a mesh-based multicore NoC architecture. We describe an optimised ray tracing kernel and parallelisation strategies, varying the workload distribution statically and dynamically. In this work, we present results and timing performance of our parallel ray tracing application on a NoC, which are obtained through our cycle accurate multicore NoC simulator. Using a dynamic scheduling load balancing technique, we achieved a maximum speedup multiplier of 35.97 on an 8 6 8 networked processor array using a NoC as the interconnect.

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Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip

Cited by 23 publications

References 14 publications

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Ray tracing on a networked processor array

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