Parallel and Pipelined 2-D Median Filter Architecture

A Low-Cost Design of 2D Median Filter

“…In our design, a special parallel sorting module is proposed to reduce the pipelined registers effectively and the redundant comparison operations are removed by adopting functional sharing concept. According to the experimental results, the area cost of our architecture can save more than 30% on average when compared to the previous designs [8]- [11] on the condition of the same operating speeds.…”

“…The goal of median filter is to search the ((M +1)/2) th number among M candidate data where M is odd. To achieve higher computation speed and fulfill the real-time requirement, hardware implementation of median filters on field programmable gate arrays (FPGA) or application specific IC (ASIC) are necessary and inevitable [6]- [11].…”

“…Those previous median filter architectures can be divided into two types, the single-input based [6]- [7] and multipleinput based [8]- [11] designs. As for the single-input based median filter design, it processes one input value in each cycle.…”

“…By using the reuse property of input values, Vega-Rodríguez et al [10] proposed a high-throughput 2-D median filter architecture that can produce four median values in each cycle. Inspired by [10], J. Subramaniam et al [11] proposed 2D median filter architecture with lower access times.…”

“…However, these 2D median filters [10], [11] need larger amounts of pipelined registers and more comparison operations to finish 2D image median filtering. As the bit-width of input values increases, it will lead to a considerable increase in area cost.…”