Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA

Barranco, Francisco; Tomasi, Matteo; Díaz, Javier; Vanegas, Mauricio; Ros, Eduardo

doi:10.1109/tvlsi.2011.2145423

Cited by 58 publications

(43 citation statements)

References 33 publications

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“…The optical flow in earlier research [36] uses five frames to generate a single-level LK optical flow. Therefore, the bandwidth is reduced by 28% when compared with that in another study [24] but is still larger than that in the proposed design.…”

Section: Hardware Designmentioning

confidence: 99%

“…In another study in [32], a new benchmark for optical flow is introduced. The algorithm proposed by Barranco et al [36] uses an earlier optical flow design [24] and implements a multi-level LK algorithm. As three-tap gradient coefficients are used for the warping operation of the multi-level LK optical flow, five frames are used for the single-level generation of the LK optical flow.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Hardware Architecture of the Lucas–Kanade Optical Flow for Reduced Frame Memory Access

Seong

Rhee

Lee

2016

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-The Lucas-Kanade (LK) algorithm is a cost-efficient gradient-based algorithm for real-time optical flow generation. An excessive external memory access limits the LK algorithm from being used broadly in practical high-frame-rate applications. To overcome this limitation, this paper proposes a novel hardware architecture that stores the input image after the Gaussian filtering operation instead of the original input image itself. The Gaussian-filtered image is downsampled in both the horizontal and vertical directions, thus reducing the external memory access to one quarter of the original data. The downsampling operation does not cause a significant degradation of the accuracy because the Gaussian filter is a low-pass filter that reduces the aliasing effect of downsampling. The downsampled pixels are selected in an interleaved manner across multiple frames to reduce the degradation of the accuracy. Experimental results show that the proposed algorithm reduces the frame memory access by 61% to 75% when compared to the previous research.Index Terms-Lucas-Kanade optical flow, FPGA, VLSI, frame bandwidth 1051-8215 (c)

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Section: Hardware Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Novel Hardware Architecture of the Lucas–Kanade Optical Flow for Reduced Frame Memory Access

Seong

Rhee

Lee

2016

IEEE Trans. Circuits Syst. Video Technol.

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“…The measurement of optical flow is a crucial and challenging task in processing of video sequences, and its hardware acceleration has been regarded as critically important for low-power real-time computer vision systems [11]. We will demonstrate that the Lucas-Kanade (L-K) algorithm [12], [13], [14], an optical flow method with a relatively low computational hardware overhead and reasonably good accuracy, can be efficiently implemented in the proposed time-sharing pipeline.…”

Section: Multi-resolution Optical Flowmentioning

confidence: 99%

An energy efficient time-sharing pyramid pipeline for multi-resolution computer vision

Zhu

Garg

Tsai

et al. 2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-We introduce an energy efficient time-sharing pyramid pipeline architecture designed for multi-resolution image analysis in mobile computer vision. The time-sharing pipeline efficiently reduces the off-chip memory traffic by re-organizing the data storage and processing order of an image pyramid. We build a parameterized image pyramid hardware generator and successfully evaluate the overall pyramid design space. Our results demonstrate that the time-sharing pyramid pipeline achieves about 50% of hardware savings in terms of area and power consumption compared to the traditional linear pipeline implementation. We also implement the multi-resolution LucasKanade optical flow algorithm on the time-sharing pipeline, and demonstrate an order of magnitude savings in off-chip memory traffic and system energy consumption.

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“…In recent years, several improvements have been proposed to the classical optical flow estimators. Some of them proposed bioinspired optical flow VLSI implementations on embedded hardware [8,9], FPGAs [10][11][12] or GPUs [13]. Due to temporal restrictions in most applications, some of the methods proposed relaxed versions of the algorithm to accelerate its processing [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Real time motion estimation using a neural architecture implemented on GPUs

García-Rodríguez

Orts-Escolano

Angelopoulou

et al. 2014

J Real-Time Image Proc

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This work describes a neural network based architecture that represents and estimates object motion in videos. This architecture addresses multiple computer vision tasks such as image segmentation, object representation or characterization, motion analysis and tracking. The use of a neural network architecture allows for the simultaneous estimation of global and local motion and the representation of deformable objects. This architecture also avoids the problem of finding corresponding features while tracking moving objects. Due to the parallel nature of neural networks, the architecture has been implemented on GPUs that allows the system to meet a set of requirements such as: time constraints management, robustness, high processing speed and re-configurability. Experiments are presented that demonstrate the validity of our architecture to solve problems of mobile agents tracking and motion analysis.

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Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA

Cited by 58 publications

References 33 publications

A Novel Hardware Architecture of the Lucas–Kanade Optical Flow for Reduced Frame Memory Access

A Novel Hardware Architecture of the Lucas–Kanade Optical Flow for Reduced Frame Memory Access

An energy efficient time-sharing pyramid pipeline for multi-resolution computer vision

Real time motion estimation using a neural architecture implemented on GPUs

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