Parallel dedicated hardware devices for heterogeneous computations

Marongiu, A.; Palazzari, P.; Rosato, Vittorio

doi:10.1145/582034.582063

Cited by 3 publications

(3 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…7 shows the average duration of the OREN protocol simulation, assuming that a dedicated hardware is available for the computations. This specialized hardware helps reducing the total time of heterogeneous computations by at least a factor of six [23] when compared to general purpose CPUs (with a processing power similar to that of current CPUs found on mobile devices). As it can be seen from Fig.…”

Section: Optimality Criteriamentioning

confidence: 99%

OREN: Optimal revocations in ephemeral networks

et al. 2011

View full text Add to dashboard Cite

a b s t r a c tPublic-key certificates allow a multitude of entities to securely exchange and verify the authenticity of data. However, the ability to effectively revoke compromised or untrustworthy certificates is of great importance when coping with misbehavior. In this paper, we design a fully distributed local certificate revocation scheme for ephemeral networks -a class of extremely volatile wireless networks with short-duration and short-range communications -based on a game-theoretic approach. First, by providing incentives, we can guarantee the successful revocation of the malicious nodes even if they collude. Second, thanks to the records of past behavior, we dynamically adapt the parameters to nodes' reputations and establish the optimal Nash equilibrium (NE) on-the-fly, minimizing the social cost of the revocation. Third, based on the analytical results, we define OREN, a unique optimal NE selection protocol, and evaluate its performance through simulations. We show that our scheme is effective in quickly and efficiently removing malicious devices from the network.

show abstract

Section: Optimality Criteriamentioning

confidence: 99%

OREN: Optimal revocations in ephemeral networks

et al. 2011

View full text Add to dashboard Cite

show abstract

“…Ylichron (now PLDA Italia) developed a source-to-source C to VHDL compiler toolchain targeting system designers called HCE (Hardware Compiling Environment). The HCE toolchain [29] takes ANSI-C language as input, which describes the hardware architecture with some limitations and extensions. ROCCC 2.0 [23] is a free and open source tool that focuses on FPGAbased code acceleration from a subset of the C language.…”

Section: Application Specific Hardware Accelerator (Asha)mentioning

confidence: 99%

“…To improve HLS based multi-ASHA system performance an intelligent controller is needed that has efficient on-chip Scratchpad Memory and Data Manager, intelligent front-end/back-end Scheduler, fast SSSI link and supports programming model that manages memory accesses in software so that hardware can best utilize them. A PMC based controller with the above mentioned features is integrated with an HLS HCE [29] tool called Advanced Multi-accelerator Controller (AMC). AMC permits HLS programmers to write ASHA with data access patterns that eliminate the requirement of extra core for data transfer and data management.…”

Section: Amc: Advanced Multi-accelerator Controllermentioning

confidence: 99%

A novel access pattern-based multi-core memory architecture

Hussain¹

View full text Add to dashboard Cite

Increasingly High-Performance Computing (HPC) applications run on heterogeneous multi-core platforms. The basic reason of the growing popularity of these architectures is their low power consumption, and high throughput oriented nature. However, this throughput imposes a requirement on the data to be supplied in a high throughput manner for the multi-core system. This results in the necessity of an efficient management of on-chip and off-chip memory data transfers, which is a significant challenge. Complex regular and irregular memory data transfer patterns are becoming widely dominant for a range of application domains including the scientific, image and signal processing. Data accesses can be arranged in independent patterns that an efficient memory management can exploit. The software based approaches using general purpose caches and on-chip memories are beneficial to some extent. However, the task of efficient data management for the throughput oriented devices could be improved by providing hardware mechanisms that exploit the knowledge of access patterns in memory management and scheduling of accesses for a heterogeneous multi-core architecture. The focus of this thesis is to present architectural explorations for a novel access pattern-based multi-core memory architecture. In general, the thesis covers four main aspects of memory system in this research. These aspects can be categorized as: i) Uni-core Memory System for Regular Data Pattern. ii) Multi-core Memory System for Regular Data Pattern. iii) Uni-core Memory System for Irregular Data Pattern. and iv) Multi-core Memory System for Irregular Data Pattern. Les aplicacions de computació d'alt rendiment (HPC) s'executen cada vegada més en plataformes heterogènies de múltiples nuclis. El motiu bàsic de la creixent popularitat d'aquestes arquitectures és el seu baix consum i la seva natura orientada a alt throughput. No obstant, aquest thoughput imposa el requeriment de que les dades es proporcionin al sistema també amb alt throughput. Això resulta en la necessitat de gestionar eficientment les trasferències de memòria (dins i fora del chip), un repte significatiu. Els patrons de transferències de memòria regulars però complexos així com els irregulars són cada vegada més dominants per a diversos dominis d'aplicacions, incloent el científic i el processat d'imagte i senyals. Aquests accessos a dades poden ser organitzats en patrons independents que un gestor de memòria eficient pot explotar. Els mètodes basats en programari emprant memòries cau de propòsit general i memòries al chip són beneficioses fins a cert punt. No obstant, la tasca de gestionar eficientment les transferències de dades per a dispositius orientats a throughput pot ser millorada oferint mecanismes hardware que explotin el coneixement dels patrons d'accés de les aplicacions, així com la planificació dels accessos a una arquitectura de múltiples nuclis. Aquesta tesis està enfocada a explorar una arquitectura de memòria novedosa per a processadors de múltiples nuclis, basada en els patrons d'accés. En general, la recerca de la tesis cobreix quatres aspectes principals del sistema de memòria. Aquests aspectes són: i) sistema de memòria per a un únic nucli amb patrons regulars, ii) sistema de memòria per a múltiples nuclis amb patrons regulars, iii) sistema de memòria per a un únic nucli amb patrons irregulars, iv) sistema de memòria per a múltiples nuclis amb patrons irregulars.

show abstract