Parallel digital neural hardware for controller design

Neusser, S.; Höfflinger, B.

doi:10.1016/0378-4754(95)00067-4

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2012

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“…Feed-forward hardware architecture. The parallelism of an ANN can be divided into 3 levels: layers, neurons and synapses [7]. Previous works usually try to save silicon area by using serial architecture in forward process [8], but somehow harm the parallelism of ANNs.…”

Section: Hardware Architecturementioning

confidence: 99%

IP Core Based Hardware Implementation of Multi-Layer Perceptrons on FPGAs: A Parallel Approach

2012

AMR

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There’re many models derived from the famous bio-inspired artificial neural network (ANN). Among them, multi-layer perceptron (MLP) is widely used as a universal function approximator. With the development of EDA and recent research work, we are able to use rapid and convenient method to generate hardware implementation of MLP on FPGAs through pre-designed IP cores. In the mean time, we focus on achieving the inherent parallelism of neural networks. In this paper, we firstly propose the hardware architecture of modular IP cores. Then, a parallel MLP is devised as an example. At last, some conclusions are made.

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Section: Hardware Architecturementioning

confidence: 99%

IP Core Based Hardware Implementation of Multi-Layer Perceptrons on FPGAs: A Parallel Approach

2012

AMR

View full text Add to dashboard Cite

show abstract

Parallel digital neural hardware for controller design

Cited by 1 publication

References 12 publications

IP Core Based Hardware Implementation of Multi-Layer Perceptrons on FPGAs: A Parallel Approach

IP Core Based Hardware Implementation of Multi-Layer Perceptrons on FPGAs: A Parallel Approach

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