Parallel discrete event simulation on shared-memory multiprocessors

Konas, Pavlos; Yew, Pen-Chung

doi:10.1145/106073.106111

Cited by 4 publications

(3 citation statements)

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“…Shared memory implementations of conservative algorithms make possible several optimizations [4,6,11]. For example, deadlock avoidance can be implemented by having a process which is about to block on an empty link directly inspect the local clock of the process at the other end of the link.…”

Section: Conservative Distributed Algorithmsmentioning

confidence: 99%

Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms

1993

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In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardware models written in VHDL. We survey central event queue, conservative distributed and optimistic distributed PDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of these algorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at the University of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. We present measurements taken from this kernel simulating some benchmark models. It appears that this technique, which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktop multiprocessor workstations), simulating behavioral and register transfer level models. However, the degree of useful parallelism achievable on gate level models with this technique appears to be limited.

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Section: Conservative Distributed Algorithmsmentioning

confidence: 99%

Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms

1993

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“…For partitioning purposes, the simulation model is represented as a graph, where every vertex is a simulation object and every edge represents the fact that the two objects communicate during the simulation. A graph partitioning tool is then used to partition the graph to minimize the cut size (to reduce communication) while maintaining balanced partition sizes (to maintain load balancing) [42,39].…”

Section: Introductionmentioning

confidence: 99%

Scalable Algorithms for Parallel Discrete Event Simulation Systems in Multicore Environments

Ponomarev¹,

Abu-Ghazaleh²

2013

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The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. SUPPLEMENTARY NOTES ABSTRACTThis project investigated techniques for improving performance and scalability of parallel discrete event simulation systems on multicore and manycore processors and clusters of multicores. Specifically, we designed and optimized a multithreaded version of ROSS simulator to efficiently execute in these environments. In addition, we also investigated efficient model partitioning schemes and also studies techniques for improving simulation resiliency to the presence of external interference. Finally, we evaluated PDES performance on the Tilera architecture and proposed optimization techniques for that environment. 15. SUBJECT TERMS parallel discrete event simulation, multi-core algorithms, Time Warp, Tilera, optimistic simulation, shared memory communication, ROSS, model partitioning, dynamic mapping 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT SAR 18. NUMBER OF PAGES 116 19a. NAME OF RESPONSIBLE PERSON RYAN LULEY a. REPORT U b. ABSTRACT U c. THIS PAGE U 19b. TELEPONE NUMBER (Include area code) N/A Standard Form 298 (Rev. 8-98) Prescribed by ANSI Std. Z39.18

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Section: Introductionmentioning

confidence: 99%

Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation

Bahulkar

Wang

Abu-Ghazaleh

et al. 2012

2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation

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Abstract-Partitioning plays an important role in PDES performance due to the high communication cost in parallel platforms and the fine-granularity of most simulation models. Traditionally, models are partitioned by deriving the static communication graph of objects and applying graph partitioning to reduce the mincut while load balancing the number of objects. However, many, if not all, models exhibit great diversity in their dynamic behavior: objects communicate with each other with diverse frequencies that are commonly power-law distributed. Similar diversity exists in the activity of objects and the processing requirements of events. In this paper, we argue that partitioning based on static graphs ignores these effects, leading to poor partitioning. We explore how partitioning based on dynamic information should be approached and explore policies that focus on communication cost, load balancing and both. We show that on multicore clusters, dynamic partitioning achieves up to 4x better performance than static partitioning. On the AMD magnycours, where the communication latency is low, dynamic partitioning results in a 2x performance improvement over static partitioning for some of our models. Our future work considers how to derive the dynamic weights (in this study, we do that through profiling), and how to balance the importance of communication and computation in a way that is informed by the underlying architecture.

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Parallel discrete event simulation on shared-memory multiprocessors

Cited by 4 publications

References 0 publications

Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms

Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms

Scalable Algorithms for Parallel Discrete Event Simulation Systems in Multicore Environments

Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation

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