Parallel FFT Algorithms on Network-on-Chips

Bahn, Jun Ho; Yang, Jung Sook; Hu, Wen-Hsiang; Bagherzadeh, Nader

doi:10.1142/s0218126609005046

Cited by 7 publications

(10 citation statements)

References 5 publications

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“…We have evaluated our mapping and code generation method on a platooning automotive application described in [37], and on a parallel Cooley-Tukey implementation of the integer 1D radix 2 FFT over 2 14 samples [38]. We chose these two applications because they allow the computation of tight lower bounds on the execution cycle makespan and because for the FFT the cited reference provides a mapping onto NoC-based 2D tiled MPPAs.…”

Section: Resultsmentioning

confidence: 99%

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Reconciling performance and predictability on a many-core through off-line mapping

Carle

Djemal

Genius

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-We start from a general-purpose many-core architecture designed for average-case performance and ease of use. In particular, its distributed shared memory programming model allows the use of a code generation flow based on the (unmodified) gcc compiler chain. We modify this architecture and extend the code generation flow to allow the construction of efficient hard real-time systems starting from dependent task specifications. We rely on a static (off-line) real-time scheduling paradigm welladapted to embedded control and signal processing applications with regular control structure.We modify the architecture (and in particular the on-chip network) to allow the implementation of static schedules with very high (clock cycle) temporal precision. On the software side, we define application mapping rules ensuring that the timing precision provided by the hardware is not lost. These mapping rules include requirements on the allocation of data variables to specific RAM banks and on the use of locks to ensure the absence of contentions during access to shared resources. Applications complying with these rules can be written manually or automatically obtained using a new mapping tool that takes all the allocation and scheduling decisions. Compilation of the resulting C code is still done using the (unmodified) gcc compiler chain. The resulting platform provides good performance, and at the same provides very high timing precision, as shown by two case studies (an embedded controller and an implementation of the FFT).We conclude our paper with a presentation of some ongoing work on the subject: A case study (an implementation of the H.264 decoder) meant to test the limitations of our method.

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Section: Resultsmentioning

confidence: 99%

“…For the FFT example, we have also compared the measured makespan of our code with that of a classical NoC-based parallel implementation of the FFT [38] running on our architecture. For our code, the NoC was statically scheduled, while for the classical implementation it was not.…”

Section: Resultsmentioning

confidence: 99%

Reconciling performance and predictability on a many-core through off-line mapping

Carle

Djemal

Genius

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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“…The 8 following rules are used as constraint constructors for both optimization and schedulability problems. Note that considering only rules [1], [2], [3], and [8] corresponds to encoding of single-period, non-dependent tasks.…”

Section: Single-period Dependent Tasks Heterogenous Architecturementioning

confidence: 99%

“…To account for the multi-period case, the upper bound for Start(τ ) is set to T(τ )−1 for all τ . Among the constraints, we use unmodified rule [1]. Rules [4]- [7] are not used here, because we have no dependencies.…”

Section: Multi-period Non-preemptive Non-dependent Tasksmentioning

confidence: 99%

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On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling

Gorcitz

Kofman

Carle

et al. 2015

Lecture Notes in Computer Science

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Abstract. Recent papers have reported on successful application of constraint solving techniques to off-line real-time scheduling problems, with realistic size and complexity. Success allegedly came for two reasons: major recent advances in solvers efficiency and use of optimized, problemspecific constraint representations. Our current objective is to assess further the range of applicability and the scalability of such constraint solving techniques based on a more general and agnostic evaluation campaign. For this, we have considered a large number of synthetic scheduling problems and a few real-life ones, and attempted to solve them using 3 state-of-the-art solvers, namely CPLEX, Yices2, and MiniZinc/G12. Our findings were that, for all problems considered, constraint solving does scale to a certain limit, then diverges rapidly. This limit greatly depends on the specificity of the scheduling problem type. All experimental data (synthetic task systems, SMT/ILP models) are provided so as to allow experimental reproducibility.

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Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

Prasad

Chattopadhyay

Chakrabarti

2015

Microprocessors and Microsystems

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Parallel FFT Algorithms on Network-on-Chips

Abstract: Abstract

Cited by 7 publications

References 5 publications

Reconciling performance and predictability on a many-core through off-line mapping

Reconciling performance and predictability on a many-core through off-line mapping

On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

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