Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors

Cabaret, Laurent; Lacassagne, Lionel; Etiemble, Daniel

doi:10.1007/s11554-016-0574-2

Cited by 22 publications

(26 citation statements)

References 25 publications

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“…Two datasets of black and white random noise images have been generated to stress how the behavior of algorithms varies with the percentage of foreground pixels (density) and minimum size of foreground blocks (granularity) [21]. Resolution is 2048 × 2048 for two-dimensional images, and 256 × 256 × 256 for three-dimensional volumes.…”

Section: Random Synthetic Imagesmentioning

confidence: 99%

“…In the last years, the fast advance of Graphic Processing Units (GPUs) encouraged the development of algorithms specifically designed to work in a data parallel environment. So, along with sequential solutions [16], [17], [18], [19], many novel algorithms exploiting the parallelism of both CPUs and GPUs have been proposed [20], [21], [22], [23], [24].…”

Section: Introductionmentioning

confidence: 99%

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Optimized Block-Based Algorithms to Label Connected Components on GPUs

Allegretti

Bolelli

Grana

2020

IEEE Trans. Parallel Distrib. Syst.

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Connected Components Labeling (CCL) is a crucial step of several image processing and computer vision pipelines. Many efficient sequential strategies exist, among which one of the most effective is the use of a block-based mask to drastically cut the number of memory accesses. In the last decade, aided by the fast development of Graphics Processing Units (GPUs), a lot of data parallel CCL algorithms have been proposed along with sequential ones. Applications that entirely run in GPU can benefit from parallel implementations of CCL that allow to avoid expensive memory transfers between host and device. In this paper, two new eight-connectivity CCL algorithms are proposed, namely Block-based Union Find (BUF) and Block-based Komura Equivalence (BKE). These algorithms optimize existing GPU solutions introducing a block-based approach. Extensions for three-dimensional datasets are also discussed. In order to produce a fair comparison with previously proposed alternatives, YACCLAB, a public CCL benchmarking framework, has been extended and made suitable for evaluating also GPU algorithms. Moreover, three-dimensional datasets have been added to its collection. Experimental results on real cases and synthetically generated datasets demonstrate the superiority of the new proposals with respect to state-of-the-art, both on 2D and 3D scenarios.

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Section: Random Synthetic Imagesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimized Block-Based Algorithms to Label Connected Components on GPUs

Allegretti

Bolelli

Grana

2020

IEEE Trans. Parallel Distrib. Syst.

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“…The GPU-based CCL algorithms should address the data-dependent issues. Cabaret et al [39] benchmarked the existing GPU-based CCL algorithms and concluded they were all multi-pass data-independent approaches, which were not suitable for GPU acceleration. Instead of GPU programming technology, they utilized OpenMP to program a parallel version of CCL on multi-core processors.…”

Section: The Gpu-accelerated Frameworkmentioning

confidence: 99%

GPU-Accelerated Foreground Segmentation and Labeling for Real-Time Video Surveillance

Song

Tian

Fong³

et al. 2016

Sustainability

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Real-time and accurate background modeling is an important researching topic in the fields of remote monitoring and video surveillance. Meanwhile, effective foreground detection is a preliminary requirement and decision-making basis for sustainable energy management, especially in smart meters. The environment monitoring results provide a decision-making basis for energy-saving strategies. For real-time moving object detection in video, this paper applies a parallel computing technology to develop a feedback foreground-background segmentation method and a parallel connected component labeling (PCCL) algorithm. In the background modeling method, pixel-wise color histograms in graphics processing unit (GPU) memory is generated from sequential images. If a pixel color in the current image does not locate around the peaks of its histogram, it is segmented as a foreground pixel. From the foreground segmentation results, a PCCL algorithm is proposed to cluster the foreground pixels into several groups in order to distinguish separate blobs. Because the noisy spot and sparkle in the foreground segmentation results always contain a small quantity of pixels, the small blobs are removed as noise in order to refine the segmentation results. The proposed GPU-based image processing algorithms are implemented using the compute unified device architecture (CUDA) toolkit. The testing results show a significant enhancement in both speed and accuracy.

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“…The latter has the same size of the input image and contains the labels assigned to the input pixels.Several attempts to improve the performance of these algorithms were presented in the recent past. They exploit parallelism by means of either multi-core processors and Graphics Processing Units (GPUs) [5,[27][28][29][30][31] or custom hardware architectures [10,11,[14][15][16][17][18][19][20][21][22][23]26]. As it is well known, for many consumer applications, like those related to the Internet of things (IoT), reaching high speed is as important as achieving low cost and high energy efficiency [16,32].…”

mentioning

confidence: 99%

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

2020

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Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors. For purposes of comparison with existing designs, several hardware implementations are characterized for different image sizes and realization platforms. The obtained results demonstrate that frame rates and resource efficiency significantly higher than existing counterparts are achieved. The proposed hardware architecture is purposely designed to comply with the fourth generation of the advanced extensible interface (AXI4) protocol and to store intermediate and final outputs within an off-chip memory. Therefore, it can be directly integrated as a custom accelerator in virtually any modern heterogeneous embedded system-on-chip (SoC). As an example, when integrated within the Xilinx Zynq-7000 X C7Z020 SoC, the novel design processes more than 1.9 pixels per clock cycle, thus furnishing more than 30 2k × 2k labeled frames per second by using 3688 Look-Up Tables (LUTs), 1415 Flip Flops (FFs), and 10 kb of on-chip memory.

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Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors

Cited by 22 publications

References 25 publications

Optimized Block-Based Algorithms to Label Connected Components on GPUs

Optimized Block-Based Algorithms to Label Connected Components on GPUs

GPU-Accelerated Foreground Segmentation and Labeling for Real-Time Video Surveillance

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

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