Parallel LU factorization of sparse matrices on FPGA‐based configurable computing engines

Abstract

Configurable computing, where hardware resources are configured appropriately to match specific hardware designs, has recently demonstrated its ability to significantly improve performance for a wide range of computation-intensive applications. With steady advances in silicon technology, as predicted by Moore's Law, FieldProgrammable Gate Array (FPGA) technologies have enabled the implementation of System-On-a-Programmable-Chip (SOPC or SOC) computing platforms, which, in turn, have given a significant boost to the field of configurable computing. It is possible to implement various specialized parallel machines in a single silicon chip. In this paper, we describe our design and implementation of a parallel machine on an SOPC development board, using multiple instances of a soft IP configurable processor; we use this machine for LU factorization. LU factorization is widely used in engineering and science to solve efficiently large systems of linear equations. Our implementation facilitates the efficient solution of linear equations at a cost much lower than that of supercomputers and networks of workstations. The intricacies of our FPGA-based design are presented along with tradeoff choices made for the purpose of illustration. Performance results prove the viability of our approach.

Performance optimization of an FPGA-based configurable multiprocessor for matrix operations

“…Figure 1 shows our processor-based system model for the parallel BDB LU factorization algorithm [7]. The binary tree interconnection network matches well the data communication model in our algorithm.…”

“…The Shared RAM between two neighbors speeds up the system performance by eliminating the transfer of large blocks of data between memories. The sizes of the Shared RAM and Data Memory are determined based on the size of the largest 3-block matrix group that may appear in our algorithm [7] and the total available on-chip memory. We assign just enough space to the Boot ROM, Data Memory and Shared RAM in order to leave as much space as possible for the Program Memory.…”

“…We implemented the floating-point arithmetic and these functions in hardware, and interfaced the application code as custom instructions [7]. Such hardware customization also releases many resources to the processor for other tasks.…”

“…Let us begin with the preprocessing phase where we attempt to order the matrix into an optimal BDB matrix [7]. The best ordering is the one that keeps the 3-block groups as dense as possible while not making the last block too large.…”

“…[6] presents a recent example. We implemented a scalable shared-memory multiprocessor and mapped a parallel LU factorization algorithm onto an FPGA [7]. With its good performance, our machine shows the great potential of FPGA-based configurable technology for implementing parallel systems.…”