Parallel processing intensive digital front-end for IEEE 802.11ac receiver

Tafreshi, Mona Aghababaee; Yli‐Kaakinen, Juha; Levanen, Toni; Korhonen, Ville; Jääskeläinen, Pekka; Renfors, Markku; Valkama, Mikko; Takala, Jarmo

doi:10.1109/acssc.2015.7421422

Cited by 4 publications

(3 citation statements)

References 4 publications

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“…The ADC outputs, out_ADC_real and out_ADC_imag, were fed to the DFE circuitry as the in-phase and quadrature inputs, respectively. (2,14) after out_ADC_real, for instance, denotes 2 integer bits and 14 fractional bits. Four outputs, in-phase and quadrature outputs for carrier1 and carrier2, exist for the four CSFs.…”

Section: Fir1 (Cic Filter)mentioning

confidence: 99%

“…In [13], a digital down-converter with polyphase cascaded integrator comb filters is simulated to validate its compatibility with the time interleaved analog-to-digital converter. Parallel processing is employed in the channelization for an IEEE 802.11ac receiver in [14], which is implemented in software on a graphics processing unit. A lower-error Farrow structured variable fractional delay interpolation is described and simulated in [15].…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

et al. 2021

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A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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Section: Fir1 (Cic Filter)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

et al. 2021

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“…Complete software implementation of the DFE Rx for IEEE 802.11ac receiver is realized by adopting parallel processing of multiple bands in [13]. A representative example of the DFE Rx for multimode cellular transceivers is presented in [14] with simulation results.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Digital Front-End With Digital Compensation for Low-Complexity 4G Radio Transceivers

Park

Gim

Park³

et al. 2021

IEEE Access

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A digital front-end with digital compensation is designed and implemented for lowcomplexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a > 40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.

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Optimization of parallel processing intensive digital front-end for IEEE 802.11ac receiver

Yli‐Kaakinen

Levanen

Aghababaeetafreshi

et al. 2016

2016 24th European Signal Processing Conference (EUSIPCO)

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Parallel processing intensive digital front-end for IEEE 802.11ac receiver

Cited by 4 publications

References 4 publications

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Design and Implementation of a Digital Front-End With Digital Compensation for Low-Complexity 4G Radio Transceivers

Optimization of parallel processing intensive digital front-end for IEEE 802.11ac receiver

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