Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

Paulin, Pierre; Pilkington, Chuck; Langevin, M.; Bensoudane, E.; Nicolescu, Gabriela

doi:10.1145/1016720.1016735

Cited by 50 publications

(37 citation statements)

References 15 publications

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“…In order to support these features they embed hardware dedicated to inter-processor communication and synchronization. Programming models based on shared memory weak consistency models, relying on synchronization primitives are among the most popular ones [18,3,19,2]. In this case, the programmer is provided with user-level software routines, which build on hardware-supplied synchronization instructions.…”

Section: Background and Related Workmentioning

confidence: 99%

“…Issues of structured programming models and synchronization in MPSoC has been only recently faced in [2,19,14]. In [2], synchronization is provided by ad hoc semaphore unit, and caching of semaphores is adopted to reduce synchronization contention.…”

Section: Background and Related Workmentioning

confidence: 99%

“…Cache coherency is enforced by using a modified version of the MESI write-invalidate snoopy coherency protocol. Paulin et al [19] face problems related to parallel programming model design in embedded multiprocessors. The authors propose a SMP programming model based on a hardware unit, the Concurrency Engine and a software layer, which exposes to the programmer synchronization hardware by means of a C++ API.…”

Section: Background and Related Workmentioning

confidence: 99%

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An efficient synchronization technique for multiprocessor systems on-chip

Monchiero

Palermo

Silvano

et al. 2005

SIGARCH Comput. Archit. News

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Section: Background and Related Workmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

An efficient synchronization technique for multiprocessor systems on-chip

Monchiero

Palermo

Silvano

et al. 2005

SIGARCH Comput. Archit. News

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show abstract

“…Based on the trends, we identify the following three requirements for the on-chip interconnect: 1) Due to the diversity in origin and requirements, the interconnect must accommodate multiple communication paradigms and programming models [19,29].…”

Section: Introductionmentioning

confidence: 99%

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

Hansson

Goossens

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication paradigms, programming models, and interface protocols that the on-chip interconnect must accommodate.Traditionally, on-chip buses offer distributed shared memory communication with established memory-consistency models, but are tightly coupled to a specific interface protocol. On-chip networks, on the other hand, offer layering and interface abstraction, but are centred around point-topoint streaming communication, and do not address issues at the higher layers in the protocol stack, such as memoryconsistency models and message-dependent deadlock.In this work we introduce an on-chip interconnect and protocol stack that combines streaming and distributed shared memory communication. The proposed interconnect offers an established memory-consistency model and does not restrict any higher-level protocol dependencies. We present the protocol stack and the architectural blocks and quantify the cost, both on the block level and for a complete SoC. For a multi-processor multi-application SoC with multiple communication paradigms and programming models, our proposed interconnect occupies only 4% of the chip area.

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“…However, it requires support by a heavy OS-kernel such as Linux SMP, which makes it impractical to be mapped on a resource-limited embedded system. MultiFlex [9] is a multi-processor programming environment, which can support a message passing model and a shared-memory symmetric multiprocessing model (SMP). In order to be used in a resourceconstrained system, MultiFlex is implemented by a combination of a light-weight software layer and a hardware concurrency engine, which is similar to our system organization.…”

Section: Related Workmentioning

confidence: 99%

A Light-Weight Cooperative Multi-threading with Hardware Supported Thread-Management on an Embedded Multi-Processor System

Lai¹,

Schaumont

Verbauwhede

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.

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This paper proposes a light-weight cooperative multithreading programming model for an embedded multiprocessor system. The synchronization between different threads is obtained by a test-and-set-lock. Each processor needs to acquire the lock before accessing shared resources. To reduce the overhead of software thread-management, a hardware thread-queue manager is added to maintain the stack pointer for each thread. This reduces off-chip memory accesses during context switches. The whole multi-processor system, including software stack and hardware architecture, is evaluated with a cycle-accurate simulation platform. With a data-flow-based image encoder as the driver application, the multi-processor system with hardware thread-queue manager achieves 9.5% performance speedup compared to a pure software thread-queue manager.

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Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

Cited by 50 publications

References 15 publications

An efficient synchronization technique for multiprocessor systems on-chip

An efficient synchronization technique for multiprocessor systems on-chip

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

A Light-Weight Cooperative Multi-threading with Hardware Supported Thread-Management on an Embedded Multi-Processor System

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