Parallel-stage decoupled software pipelining

Abstract

In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and new applications to make effective use of CMPs, it is desirable that compilers automatically extract thread-level parallelism from single-threaded applications. DOALL is a popular automatic technique for looplevel parallelization employed successfully in the domains of scientific and numeric computing. While DOALL generally scales well with the number of iterations of the loop, its applicability is limited by the presence of loop-carried dependences. A parallelization technique with greater applicability is decoupled software pipelining (DSWP), which parallelizes loops even in the presence of loopcarried dependences. However, the scalability of DSWP is limited by the size of the loop body and the number of recurrences it contains, which are usually smaller than the loop iteration count.This work proposes a novel non-speculative compiler parallelization technique called parallel-stage decoupled software pipelining (PS-DSWP). The goal of PS-DSWP is to combine the applicability of DSWP with the scalability of DOALL parallelization. A key insight of PS-DSWP is that, after isolating the recurrences in their own stages in DSWP, portions of the loop suitable for DOALL parallelization may be exposed. PS-DSWP extends DSWP to benefit from these opportunities, utilizing multiple threads to execute the same stage of a DSWPed loop in parallel. This paper describes the PS-DSWP transformation in detail and discusses its implementation in a research compiler. PS-DSWP produces an average speedup of 114% (up to a maximum of 155%) with 6 threads on loops from a set of 5 applications. Our experiments also demonstrate that PS-DSWP achieves better scalability with the number of threads than DSWP.

Speculative separation for privatization and reductions

“…We exclude those as well, since they are limited by DOALL, not by Privateer. More powerful parallelizing transformations, such as PS-DSWP [20] will be investigated in future work.…”

A catalog of stream processing optimizations

“…When the language is not designed for fission, safety must be established either by static or by dynamic dependence analysis. An example for a static analysis that discovers fission opportunities is parallel-stage decoupled software pipelining [Raman et al 2008]. An example for a dynamic analysis that discovers fission opportunities is [Thies et al 2007].…”

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

“…However, its scalability is limited. The approach proposed by Raman et al [69] uses non-speculative parallelization pipeline, named parallel-stage decoupled software pipelining (PS-DSWP), which integrates the ability of DSWP and DOALL parallelization. By isolating some recurrences in the same stage, the approach can achieve more parallelism.…”