Parallel test reduces cost of test more effectively than just a cheap tester

Rivoir, Jochen

doi:10.1109/iemt.2004.1321674

Cited by 36 publications

(13 citation statements)

References 4 publications

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“…In multi-site testing, many dies on a load-board or even on a wafer are tested in parallel by the same ATE [1], [2], [3], [4], [5]. All the dies receive identical input by the ATE, but the output side of the die-under-test cannot be handled in the same straightforward way, as the defective dies will respond in many different, unpredictable ways.…”

Section: Introductionmentioning

confidence: 99%

A diagnosis algorithm for extreme space compaction

Holst¹

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builtin self-test (BIST) and multi-site testing are quite effective cost reduction techniques which may make diagnosis more complex. This paper presents a test response compaction scheme and a corresponding diagnosis algorithm which are especially suited for BIST and multi-site testing. The experimental results on industrial designs show, that test time and response data volume reduces significantly and the diagnostic resolution even improves with this scheme. A comparison with X-Compact indicates, that simple parity information provides higher diagnostic resolution per response data bit than more complex signatures.

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Section: Introductionmentioning

confidence: 99%

A diagnosis algorithm for extreme space compaction

Holst¹

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…In the digital domain, there has been many strides to parallelize tests because parallelization makes testing economical [3]. However, until recently, very little was done to parallelize measurements of analog DC quantities like currents and voltages.…”

Section: Introductionmentioning

confidence: 99%

Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current

Acharyya¹,

Miyao²,

Ting³

et al. 2011

2011 IEEE International Test Conference

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With advancing technology nodes, the feature sizes of transistors are scaled down aggressively and the effects of process variations on semiconductor device parameters are becoming worse. Accurate device level statistical models are necessary to understand the composite effect of process variations on IC performance. Statistical models require a large amount of data from measurements made on wafers with test structures and product chips. High precision DC parametric measurements form a key component to understanding the device level process interactions. One important aspect of DC parametric measurements is the ability to accurately measure currents ranging from pico-amperes for leakage characterization to milli-amperes for transistor IV characterization. Sophisticated test equipment that meets the requirements of high accuracy and high throughput are needed for this purpose. In this paper we present a hybrid tester that addresses these requirements. The novel architecture presented here is scalable and truly parallel. The system is capable of measuring currents from pico-amperes to hundreds of milli-amperes and at the same time provide advanced digital test capabilities.

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“…To reduce these costs and the period of a cycle, it is preferable to increase the parallel test capacity of the probe card rather than to purchase the expensive Automatic Test Equipment (ATE) [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

NAC Measurement Technique on High Parallelism Probe Card with Protection Resistors

Kim¹,

Nah²

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a novel time-domain measurement technique on a high parallelism probe card with protection resistors installed is proposed. The measured signal amplitude decreases when the measurement is performed by Needle Auto Calibration (NAC) probing on a high parallelism probe card with installed resistors. Therefore, the original signals must be carefully reconstructed, and the compensation coefficient, which is related to the number of channel branches and the value of protection resistors, must be introduced. The accuracy of the reconstructed signals is analyzed based on the varying number of channel branches and various protection resistances. The results demonstrate that the proposed technique is appropriate for evaluating the overall signal performance of probe cards with Automatic Test Equipment (ATE), which enhances the efficiency of probe card performance test dramatically.

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Parallel test reduces cost of test more effectively than just a cheap tester

Cited by 36 publications

References 4 publications

A diagnosis algorithm for extreme space compaction

A diagnosis algorithm for extreme space compaction

Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current

NAC Measurement Technique on High Parallelism Probe Card with Protection Resistors

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