2005
DOI: 10.1109/mc.2005.239
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Parallelism and the ARM instruction set architecture

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Cited by 83 publications
(28 citation statements)
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“…In this paper we assume negligible delay associated to inter-processor communication and a uniform memory model for the processors. This models fits well the behavior of a cache-coherent, shared memory single-chip multiprocessor, such as the ARM MPCore [18].…”
Section: Definition 2 a Repetition Vector Of An Sdfg=(ad) Is A Funcsupporting
confidence: 58%
“…In this paper we assume negligible delay associated to inter-processor communication and a uniform memory model for the processors. This models fits well the behavior of a cache-coherent, shared memory single-chip multiprocessor, such as the ARM MPCore [18].…”
Section: Definition 2 a Repetition Vector Of An Sdfg=(ad) Is A Funcsupporting
confidence: 58%
“…This article uses fuzzy evaluation method, first make clear the evaluation of the evaluation factor set F, then we make the evaluation index factors as m, and then we can get [7] Then we have to determine the evaluation set of indicators corresponding to the evaluation factor W, and the evaluation level is determined as n, then we can get [8] …”
Section: Literature Overview and Research Methodsmentioning
confidence: 99%
“…This article uses fuzzy evaluation method, first make clear the evaluation of the evaluation factor set F, then we make the evaluation index factors as m, and then we can get [7] 1 2 , ,…”
Section: Literature Overview and Research Methodsmentioning
confidence: 99%