Free-Space Laser Communications XXXIV 2022
DOI: 10.1117/12.2608235
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Parallelized convolutional interleaver implementation for efficient DDR memory access

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Cited by 2 publications
(2 citation statements)
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“…This appendix includes a series of derivations for the modulus and quotient calculations of 𝑓(𝑗). The recursive relation for the remainder of 𝑓(𝑗) with a step size 𝑛 for π‘š = log (𝑀) is given as π‘Ÿ (𝑗 + 𝑛) = 𝑓(𝑗 + 𝑛) mod π‘š = 𝑓(𝑗) + 𝑔(𝑗) mod 𝑁 mod π‘š = [𝑓(𝑗) + 𝑔(𝑗, 𝑛)]mod π‘š = 𝑓(𝑗) mod π‘š + 𝑔(𝑗, 𝑛) mod π‘š = [π‘Ÿ (𝑗) + π‘Ÿ (𝑗, 𝑛)] mod π‘š (10) where π‘Ÿ , (𝑗) = 𝑔 (𝑗) mod m and π‘Ÿ (𝑗) = 𝑓(𝑗) mod π‘š.…”
Section: Discussionmentioning
confidence: 99%
“…This appendix includes a series of derivations for the modulus and quotient calculations of 𝑓(𝑗). The recursive relation for the remainder of 𝑓(𝑗) with a step size 𝑛 for π‘š = log (𝑀) is given as π‘Ÿ (𝑗 + 𝑛) = 𝑓(𝑗 + 𝑛) mod π‘š = 𝑓(𝑗) + 𝑔(𝑗) mod 𝑁 mod π‘š = [𝑓(𝑗) + 𝑔(𝑗, 𝑛)]mod π‘š = 𝑓(𝑗) mod π‘š + 𝑔(𝑗, 𝑛) mod π‘š = [π‘Ÿ (𝑗) + π‘Ÿ (𝑗, 𝑛)] mod π‘š (10) where π‘Ÿ , (𝑗) = 𝑔 (𝑗) mod m and π‘Ÿ (𝑗) = 𝑓(𝑗) mod π‘š.…”
Section: Discussionmentioning
confidence: 99%
“…Kb is calculated from the average photon counts in the guard band and Ks is calculated from the difference of the average photon counts in the signal slots and guard band. Convolutional deinterleaving is implemented utilizing an external DDR4 memory operating at 2400 MHz 11 . The deinterleaved symbols with 3 bits per slot and the received channel statistics are sent over the backplane on a high-speed serial link to the decoder FPGA.…”
Section: Fpga-based Receivermentioning
confidence: 99%