Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms

Liang, Huixin; Sinha, Sharad; Zhang, Wei

doi:10.1109/tcad.2017.2697952

Cited by 12 publications

(4 citation statements)

References 35 publications

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“…Previous work has looked to target various optimisations for PRR-based designs. Researchers have explored maximising resource utilization by optimum ordering of tasks [17], task graph based scheduling as per the underlying architecture [23], heuristics to reduce fragmentation within PRRs [12] and runtime support for elastic resource allocation [27]. However, the inherent underutilization of resources when using PRR due to spatial mapping constraints on FPGA remains the same.…”

Section: Background and Motivationmentioning

confidence: 99%

“…This module checks if the generated multi-task design can be realistically mapped onto FPGA at any single time. For the PRR, the 2D area model treats mapping as a rectangle fitting problem and tries to find a region homogeneous in both size and spatial distribution of resources to which to map each incoming task [17]. For SPM, a multidimensional model accommodating a dimension for each of the heterogeneous on-chip resources, is implemented.…”

Section: Placement Checksmentioning

confidence: 99%

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Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

Minhas

Woods

Karakonstantis

2021

J Sign Process Syst

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Whilst FPGAs have been used in cloud ecosystems, it is still extremely challenging to achieve high compute density when mapping heterogeneous multi-tasks on shared resources at runtime. This work addresses this by treating the FPGA resource as a service and employing multi-task processing at the high level, design space exploration and static off-line partitioning in order to allow more efficient mapping of heterogeneous tasks onto the FPGA. In addition, a new, comprehensive runtime functional simulator is used to evaluate the effect of various spatial and temporal constraints on both the existing and new approaches when varying system design parameters. A comprehensive suite of real high performance computing tasks was implemented on a Nallatech 385 FPGA card and show that our approach can provide on average 2.9 × and 2.3 × higher system throughput for compute and mixed intensity tasks, while 0.2 × lower for memory intensive tasks due to external memory access latency and bandwidth limitations. The work has been extended by introducing a novel scheduling scheme to enhance temporal utilization of resources when using the proposed approach. Additional results for large queues of mixed intensity tasks (compute and memory) show that the proposed partitioning and scheduling approach can provide higher than 3 × system speedup over previous schemes.

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Section: Background and Motivationmentioning

confidence: 99%

Section: Placement Checksmentioning

confidence: 99%

Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

Minhas

Woods

Karakonstantis

2021

J Sign Process Syst

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“…The final goal is to achieve high-quality fault-free placements from arbitrary initial placements. In mathematics, placement optimization is generally considered as a kind of NP-hard combination optimization problems [8]. In order to solve such problems, the computing system should have enough computational power to generate feasible solutions and an optimization algorithm is needed to select an optimal solution.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Placement Optimization for Bio-Inspired Self-Repairing Hardware

Liu

Xiao

et al. 2020

IEEE Access

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Bio-inspired self-repairing hardware is a distributed self-adaptive system, characterized by powerful fault-tolerant ability and environment adaptivity. However, it suffers from some difficulties such as large resource consumption and degraded circuit performances. From the viewpoint of cybernetics and computer science, the cellular differentiation and substitution process of bio-inspired self-repairing hardware can be converted into dynamic placement problems on a reconfigurable system. Current systems can only generate some predefined fault-free placements from a finite number of initial placements. The aim of this paper was to achieve high-quality placements from arbitrary initial placements. Based on P systems, an analysis has been made on the limitations of current systems and an improved computing system has been developed to achieve the ergodic property. Its computational power has been verified by a constructive proof. Moreover, centering on the problem how to improve the placement quality on a distributed platform, the optimization model, task allocation, optimization strategy, and membrane optimization algorithm have been designed and developed. The optimization performances were verified and the calculation amount was exhibited by experiments. Finally, it indicated by comparison that the proposed approach would reduce the resource consumption and maintain good circuit performances. INDEX TERMS Bio-inspired self-repairing hardware, dynamic placement optimization, P systems, computing model, membrane optimization algorithms.

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“…The second challenge investigates reconfiguration overhead on FPGAs [3] incurred due to multi-task execution in cloud systems. Initial work has targeted this via intelligent scheduling targeting techniques such as module reuse [4] and faster reconfiguration memories [5]. However, as per our knowledge, no work has looked into bringing more reconfiguration methods into scheduling model, particularly the more recent software based approaches.…”

Section: Introductionmentioning

confidence: 99%

Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems

Minhas

Woods

Karakonstantis

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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With FPGAs being increasingly integrated into existing software-based heterogeneous cloud environments, novel evaluation mechanisms are required to reveal the energyperformance trade-offs of accelerators (FPGAs, GPUs, etc) using high-level heterogeneous programming environments. For FP-GAs, this also requires reconsideration of scheduling policies and reconfiguration methods with an aim to integrate software-based approaches as well as optimizations for broader workload sizes. Proposed considerations are evaluated using various configuration techniques for a number of applications.

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Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms

Cited by 12 publications

References 35 publications

Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

Dynamic Placement Optimization for Bio-Inspired Self-Repairing Hardware

Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems

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