Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Abstract

Abstract-The brain-inspired spiking neural network neuromorphic architecture offers a promising solution for a wide set of cognitive computation tasks at a very low power consumption. Due to the practical feasibility of hardware implementation, we present a memristor-based model of hardware spiking neural networks which we simulate with N2S3 (Neural Network Scalable Spiking Simulator), our open source neuromorphic architecture simulator. Although Spiking neural networks are widely used in the community of computational neuroscience and neuromorphic computation, there is still a need for research on the methods to choose the optimum parameters for better recognition efficiency. With the help of our simulator, we analyze and evaluate the impact of different parameters such as number of neurons, STDP window, neuron threshold, distribution of input spikes and memristor model parameters on the MNIST hand-written digit recognition problem. We show that a careful choice of a few parameters (number of neurons, kind of synapse, STDP window and neuron threshold) can significantly improve the recognition rate on this benchmark (around 15 points of improvement for the number of neurons, a few points for the others) with a variability of 4 to 5 points of recognition rate due to the random initialization of the synaptic weights.

Neuromorphic Design Using Reward-based STDP Learning on Event-Based Reconfigurable Cluster Architecture

“…We transferred the pixel intensity into spikes. The intensity between 0 to 255 for each pixel is transferred to 0 to 22 spikes while presenting the inputs using a 350 ms presentation window based on our previous SNN simulation experiences [19,20]. To train the network with MNIST, we used Restricted Boltzmann Machine (RBM) network topology.…”

POETS: A Parallel Cluster Architecture for Spiking Neural Network

“…Spiking Neural Network is a promising approach for future computing platforms, with the ability of learning which could be used in three different scenarios:  An accelerator in GPP platforms to overcome the Von Neumann memory bottleneck, for example in robotic brains, or low-power mobile processors, [24], [25].  Direct implementation of spiking neural network on hardware, taking advantage of low-cost computing for the same purposes as ANN (e.g., Deep Learning) applications such as prediction, detection and recognition [5], [26].…”

Progressive compression and weight reinforcement for spiking neural networks

“…SNNs can handle natural signals. They can be implemented physically through ultra‐low power based devices; for instance, on CMOS 26 or memristors 2 . CMOS artificial neuron is a simple component (only six transistors operating in the subthreshold mode).…”

“…Several works were presented in the past to propose a hardware implementation of the neuromorphic architectures using different hardware components 1,2 . However, the commonly observed characteristic when dealing with SNNs is the use of large networks.…”