Parameterized tiling revisited

Baskaran, Muthu Manikandan; Hartono, Albert; Tavarageri, Sanket; Henretty, Thomas; Ramanujam, J.; Sadayappan, P.

doi:10.1145/1772954.1772983

Cited by 47 publications

(60 citation statements)

References 22 publications

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“…2 In each 3-D space, the x, y, and z axes show tile size values for the outer loop, middle loop and inner loop respectively. These tile choices are called "best" points in this section.…”

Section: Search Space Reduction By Dl/ml Modelmentioning

confidence: 99%

“…Loop Tiling [7,17,23,29,35,36] is a classical technique to enhance data reuse in memory hierarchy levels close to the processor. Recent advances have made it possible to automatically generate parametrically tiled code, even for imperfectly nested loops [2,15,18,24]. It is well known that the choice of tile sizes has a significant effect on performance, but the effective selection of optimized tile sizes remains an open problem that has become ever more challenging as processor memory hierarchies increase in complexity and depth.…”

Section: Introductionmentioning

confidence: 99%

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Analytical Bounds for Optimal Tile Size Selection

Shirako

Sharma

Fauzia

et al. 2012

Lecture Notes in Computer Science

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Abstract. In this paper, we introduce a novel approach to guide tile size selection by employing analytical models to limit empirical search within a subspace of the full search space. Two analytical models are used together: 1) an existing conservative model, based on the data footprint of a tile, which ignores intra-tile cache block replacement, and 2) an aggressive new model that assumes optimal cache block replacement within a tile. Experimental results on multiple platforms demonstrate the practical effectiveness of the approach by reducing the search space for the optimal tile size by 1,307× to 11,879× for an Intel Core-2-Quad system; 358× to 1,978× for an Intel Nehalem system; and 45× to 1,142× for an IBM Power7 system. The execution of rectangularly tiled code tuned by a search of the subspace identified by our model achieves speed-ups of up to 1.40× (Intel Core-2 Quad), 1.28× (Nehalem) and 1.19× (Power 7) relative to the best possible square tile sizes on these different processor architectures. We also demonstrate the integration of the analytical bounds with existing search optimization algorithms. Our approach not only reduces the total search time from Nelder-Mead Simplex and Parallel Rank Ordering methods by factors of up to 4.95× and 4.33×, respectively, but also finds better tile sizes that yield higher performance in tuned tiled code.

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“…2 In each 3-D space, the x, y, and z axes show tile size values for the outer loop, middle loop and inner loop respectively. These tile choices are called "best" points in this section.…”

Section: Search Space Reduction By Dl/ml Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analytical Bounds for Optimal Tile Size Selection

Shirako

Sharma

Fauzia

et al. 2012

Lecture Notes in Computer Science

Self Cite

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“…which we assume have been suitably preprocessed if necessary to make rectangular tiling legal [6], [39]. We first present an algebraic characterization for the generation of loop bounds for non-adaptive parametric tiling, using a notation similar to that used in prior work of Baskaran et al [2]. We then develop the formulation for the modified lower and upper bounds of the tile iterators as the tile sizes are changed.…”

Section: Formulation Of Dynamic Tile Size Variationmentioning

confidence: 99%

“…Two important properties of S T (details may be found in [2]) are: (1) the solutions to S ′ also satisfy S T and (2) S T is in row echelon form. Hence scanning S T will generate the tile loops (loops with tile coordinates).…”

Section: A Parametric Tilingmentioning

confidence: 99%

“…The choice of tile sizes for loops has a significant impact on the execution time of such programs. Advances in parameterized tiling, where tile sizes are symbolic parameters [2], [14], [15], [18], [19], [21], [22], [29], [37], have enabled the generation of code that can be executed with different tile sizes in different environments. There has also been much interest in developing analytical models to determine optimal tile sizes as a function of architectural parameters (sizes and associativities of caches and TLBs, etc.)…”

Section: Introductionmentioning

confidence: 99%

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Dynamic selection of tile sizes

Tavarageri

Pouchet

Ramanujam

et al. 2011

2011 18th International Conference on High Performance Computing

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Abstract-Tiling is a key program transformation to achieve effective data reuse. But the performance of tiled programs can vary considerably with different tile sizes. Hence the selection of good tile sizes is crucial.Although there has been considerable research on analytical models for selecting tile sizes, they have not been shown to be effective in finding optimal tile sizes across a range of programs and target architectures. Auto-tuning is a viable alternative that is often used in practice, and involves the execution of different combinations of tile sizes in a systematic fashion to find the best ones. But this is sometimes infeasible -for instance when the program is to be run on unknown platforms (e.g., cloud environments).We propose a novel approach for generating code to enable dynamic tile size selection, based on monitoring the performance of a few loop iterations. The selection operates at run time on the "production" run, without any a priori knowledge of the execution environment. We discuss the theory and implementation of a parametric tiled code generator that enables run-time tile size tuning and describe a search strategy to determine effective tile sizes. Experimental results demonstrate the effectiveness of the approach.

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An Analytical Model for Loop Tiling Transformation

Kelefouras

Djemame

Κεραμίδας

et al. 2022

Lecture Notes in Computer Science

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Loop tiling is a well-known loop transformation that enhances data locality in memory hierarchy. In this paper, we initially reveal two important inefficiencies of current analytical loop tiling models and we provide the theoretical background on how current analytical models can address these inefficiencies. To this end, we propose a new analytical model which is more accurate that the existing ones. We showcase, both theoretically and experimentally, that the proposed model can accurately estimate the number of cache misses for every generated tile size and as a result more efficient tile sizes are opted. Our evaluation results provide high cache misses gains and significant performance gains over gcc compiler and Pluto tool on an x86 platform.

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Parameterized tiling revisited

Cited by 47 publications

References 22 publications

Analytical Bounds for Optimal Tile Size Selection

Analytical Bounds for Optimal Tile Size Selection

Dynamic selection of tile sizes

An Analytical Model for Loop Tiling Transformation

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