Parametric Encryption Hardware Design

Masle, Adrien Le; Luk, Wayne; Eldredge, Jared; Carver, Kris

doi:10.1007/978-3-642-12133-3_9

Cited by 10 publications

(10 citation statements)

References 7 publications

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“…6, for the Montgomery multiplier, high frequency errors are localized to a few (r, p) tuples. 2 This is not the case for the exponentiation module whose average frequency error is high and close to the maximum frequency error. Here, the reference point chosen to determine f 0 ((r, p) = (1, 1)) has a maximum frequency, which is around 15% lower than for the other values of p, leading to a constant error.…”

Section: A Accuracy Of the Modelmentioning

confidence: 98%

“…Common applications falling into this category are bitwise algorithms for which the result is updated at each iteration based on the corresponding bit of one or several inputs. In cryptography, this is for instance the case of the Montgomery multiplication algorithm [14], the square-multiply exponentiation algorithm [2], and the Lucas primality test [15], [16]. Some important arithmetic algorithms, such as the integer square root [17] and the restoring division algorithms also follow this pattern.…”

Section: A Main Ideamentioning

confidence: 99%

“…These values of 1 Computed as |v − v model |/v where v is the value considered. 2 Here, the errors are computed as ( f model − f )/ f to show their directions. r and p should be avoided as they lead to pointless areaconsuming designs.…”

Section: A Accuracy Of the Modelmentioning

confidence: 99%

“…In [1], a parametric approach is developed for software-defined radio modules. In [2], we present parametric Montgomery multiplier, Montgomery exponentiator, and Miller-Rabin primality tester designs. These three functions are the core of many public-key crypto-systems.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Masle

Luk

2014

IEEE Trans. VLSI Syst.

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Abstract-This paper shows how a general form of algorithms consisting of a loop with loop dependencies carried from one iteration to the next can automatically be mapped to a parametric hardware design with pipelining and replication features. A technology-independent parametric model of the proposed design is developed to capture the variations of area and throughput with the number of pipeline stages and replications. Our model allows rapid optimization of design parameters by a few pre-synthesis operations. We present an optimization method based on the model. Our method is evaluated using three different applications implemented on a Xilinx Spartan 6 XC6SLX45T FPGA: a carry-save adder-based Montgomery multiplier, a modular exponentiation module, and an integer square root module. Our model facilitates design space exploration; it can quickly predict the area taken by our designs with less than 5% of error, and their maximum frequencies and throughputs with less than 22% of error. Our optimization method is up to 96 times faster than a full search through the design space.Index Terms-Design space exploration, field-programmable gate array (FPGA), hardware mapping, loop-carried dependencies, resource estimation.

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Section: A Accuracy Of the Modelmentioning

confidence: 98%

Section: A Main Ideamentioning

confidence: 99%

Section: A Accuracy Of the Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Mapping Loop Structures Onto Parametrized Hardware Pipelines

Masle

Luk

2014

IEEE Trans. VLSI Syst.

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“…The modular exponentiation module is based on the Montgomery multiplier presented in [18]. The square and multiply operations are both performed by the Montgomery multiplier, which makes them hardly distinguishable.…”

Section: B Study Case: Modular Exponentiationmentioning

confidence: 99%

Constant power reconfigurable computing

Masle

Chow

Luk

2011

2011 International Conference on Field-Programmable Technology

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Abstract-We present Constant Power Reconfigurable Computing, a general and device-independent framework based on a closed-loop control system used to keep the power consumption constant for any reconfigurable computing design targeting FPGA implementation. We develop an on-chip power consumer, an on-chip power monitor and a proportionalintegral-derivative controller with circuit primitives available in most commercial FPGAs. We demonstrate the effectiveness of the proposed methodology on a square-and-multiply exponentiation circuit implemented on a Spartan-6 LX45 FPGA board. By reducing the peak autocorrelation values by a factor of 2.7 on average, the proposed Constant Power Reconfigurable Computing approach decreases the information leaked by the power consumption of this system with only 26% area overhead and 28% power overhead.

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Constructing Cluster of Simple FPGA Boards for Cryptologic Computations

Doröz

Savaş

2012

Lecture Notes in Computer Science

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Parametric Encryption Hardware Design

Cited by 10 publications

References 7 publications

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Constant power reconfigurable computing

Constructing Cluster of Simple FPGA Boards for Cryptologic Computations

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