Parametric minimum hardware QR-factoriser architecture for V-BLAST detection

Sobhanmanesh, Fariborz; Nooshabadi, Saeid

doi:10.1049/ip-cds:20060060

Cited by 20 publications

(11 citation statements)

References 3 publications

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“…Therefore, the CORDIC algorithm can be applied to perform the angle calculation and rotation operations using vectoring and rotation modes of the CORDIC operations. The CORDIC-based processors can be efficiently mapped into the QR decomposition systolic array, which have been presented in [12], [13], [14], [15], [16], [17].…”

Section: Introductionmentioning

confidence: 99%

Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGA

Chen

Sima

2011

2011 International Conference on Reconfigurable Computing and FPGAs

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This paper presents a parallel architecture of an QR decomposition systolic array based on the Givens rotations algorithm on FPGA. The proposed architecture adopts a direct mapping by 21 fixed-point CORDIC-based process units that can compute the QR decomposition for an 4×4 real matrix. In order to achieve a comprehensive resource and performance evaluation, the computational error analysis, the resource utilized, and speed achieved on Virtex5 XC5VTX150T FPGA, are evaluated with the different precision of the intermediate word lengthes. The evaluation results show that 1) the proposed systolic array satisfies 99.9% correct 4 × 4 QR decomposition for the 2 −13 accuracy requirement when the word length of the data path is lager than 25-bit; 2) occupies about 2, 810 (13%) slices, and achieves about 2.06 M/sec updates by running at the maximum frequency 111 MHz.

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Section: Introductionmentioning

confidence: 99%

Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGA

Chen

Sima

2011

2011 International Conference on Reconfigurable Computing and FPGAs

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“…On the other hand the burstbased communication system that needs a preamble for synchronization purposes, e.g., in case of IEEE 802.11a WLAN-OFDM receivers, can use a single CORDIC unit configurable for both operating modes since the estimation and correction are not performed simultaneously [94], [95]. Apart from these, the CORDIC-based QR decomposition has been used in multiinput-multi-output (MIMO) systems to implement V-BLAST detectors [96]- [98], and to implement a recursive-least-square (RLS) adaptive antenna beamformer [67], [99], [100].…”

Section: ) Analog and Digital Modulationmentioning

confidence: 99%

50 Years of CORDIC: Algorithms, Architectures, and Applications

Meher

Valls

Juang

et al. 2009

IEEE Trans. Circuits Syst. I

456

198

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“…To solve for the area constraint, control logic based designs are developed which reuses the resources with reduced throughput. Parameterized control logic based architecture [10], folded systolic array based architecture [17], and CORDIC core based architecture [6] are some of the architectures discussed in the literature, which can be made scalable by changing the control logic. In this work, a 16-bit fixed point scalable QRD architecture is proposed by utilizing LUT-N method for square root and inverse root logic.…”

Section: Background and Related Workmentioning

confidence: 99%

“…There are different algorithms and architectures proposed in the literature which includes Gram-Schmidt orthogonalization, modified Gram-Schmidt orthogonalization [2,3], Givens rotation [4][5][6][7][8][9][10][11], householder transformations [12], and various other hybrid methods [13,14]. Gram-Schmidt (GS) algorithm offers reduced accuracy and stability in fixed precision environment.…”

Section: Introductionmentioning

confidence: 99%

Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

Prabhu

Johnson

Rani

2014

International Journal of Reconfigurable Computing

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A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of size × , where 4 ≤ ≤ 8 and ≥ by dynamically inserting or removing the partial modules. The evaluation results demonstrate a significant reduction in latency, area, and power as compared to other existing architectures. The functionality of the proposed core is evaluated for a variable length adaptive equalizer.

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Parametric minimum hardware QR-factoriser architecture for V-BLAST detection

Cited by 20 publications

References 3 publications

Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGA

Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGA

50 Years of CORDIC: Algorithms, Architectures, and Applications

Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

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