Parametric Mismatch Characterization for Mixed-Signal Technologies

Tuinhout, H.P.; Wils, Nicole; Andricciola, Pietro

doi:10.1109/jssc.2010.2051478

Cited by 15 publications

(4 citation statements)

References 19 publications

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“…We also performed the procedures to decide the reference voltages and bias levels. Additionally, we designed the blocks in the receiver close together and symmetrically to reduce the mismatches [1], [19].…”

Section: Inverter-based Summer and Pam-4 Decision Feedback Equalizermentioning

confidence: 99%

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

2022

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Separate inverter-based summers for each eye are introduced into the decision feedback equalizer (DFE) of a single-ended four-level amplitude modulation (PAM-4) receiver for memory interfaces. The summers increase the input swing of the slicers while maintaining the advantages of inverter-based amplifiers with higher gain and lower power consumption than current-mode logic (CML) amplifiers. The high-gain summer can improve clock-to-Q delays of slicers in the PAM-4 DFE without increasing the power consumption of the slicers. This can alleviate the timing constraint that the DFE must meet to respond correctly to the previous data. The non-linear gain of the inverter-based structure can be ignored by using separate paths depending on each eye. A prototype chip was fabricated in a 65 nm CMOS process. At 24 Gb/s, the DFE can achieve a bit error rate (BER) of 10 -12 with an eye width of 100 mUI with -7.3 dB insertion loss at Nyquist frequency and the power efficiency of 0.73 pJ/b.INDEX TERMS Four-level pulse amplitude modulation (PAM-4) receiver, inverter-based summer, memory interface

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Section: Inverter-based Summer and Pam-4 Decision Feedback Equalizermentioning

confidence: 99%

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

2022

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“…In nanotechnologies there are several new effects, which must be taken into account: poly-silicon gate morphology, litho spread, pockets or helo implants, hot carrier effects, etc. [2,5,6].…”

Section: Jinst 9 C07009mentioning

confidence: 99%

Fast and precise algorithms for calculating offset correction in single photon counting ASICs built in deep sub-micron technologies

Maj¹

2014

J. Inst.

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An important trend in the design of readout electronics working in the single photon counting mode for hybrid pixel detectors is to minimize the single pixel area without sacrificing its functionality. This is the reason why many digital and analog blocks are made with the smallest, or next to smallest, transistors possible. This causes a problem with matching among the whole pixel matrix which is acceptable by designers and, of course, it should be corrected with the use of dedicated circuitry, which, by the same rule of minimizing devices, suffers from the mismatch. Therefore, the output of such a correction circuit, controlled by an ultra-small area DAC, is not only a non-linear function, but it is also often non-monotonic. As long as it can be used for proper correction of the DC operation points inside each pixel, it is acceptable, but the time required for correction plays an important role for both chip verification and the design of a big, multi-chip system. Therefore, we present two algorithms: a precise one and a fast one. The first algorithm is based on the noise hits profiles obtained during so called threshold scan procedures. The fast correction procedure is based on the trim DACs scan and it takes less than a minute in a SPC detector systems consisting of several thousands of pixels.

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“…However, even between matched components on the same die, parametric differences are observed. These differences, indicated with the term parametric mismatch , can be divided into two categories, namely random mismatch and systematic mismatch . Random mismatch is generally attributable to microscopic device fluctuations, such as random dopant fluctuations , lithographic edge roughness , or grain boundary effects .…”

Section: Introductionmentioning

confidence: 99%

Analysis of time delay difference due to parametric mismatch in matched filter channels

Stuarts

Julián

2014

Circuit Theory & Apps

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SUMMARYThis paper presents an analysis of the time delay difference between the outputs of two matched filter channels, in the presence of parametric mismatch. A theorem for computing the cross-correlation value between two signals is developed. From the cross-correlation theorem, expressions are developed that estimate the effect of parametric mismatch in the differential time delay (DTD) for filters of arbitrary type and order and input signals of arbitrary form. The accuracy of these expressions is simulated and then demonstrated experimentally using a carefully designed setup. Filter design considerations that attempt to minimize spurious DTD in high-precision time delay estimation systems are presented.

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Parametric Mismatch Characterization for Mixed-Signal Technologies

Cited by 15 publications

References 19 publications

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

Fast and precise algorithms for calculating offset correction in single photon counting ASICs built in deep sub-micron technologies

Analysis of time delay difference due to parametric mismatch in matched filter channels

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