Parametric Throughput Oriented Large Integer Multipliers for High Level Synthesis

Abstract

The multiplication of large integers represents a significant computation effort in some cryptographic techniques. The use of dedicated hardware is an appealing solution to improve performances or efficiency. We propose a methodology to generate throughput oriented hardware accelerators for large integers multiplication leveraging High-Level Synthesis. The proposed micro-architectural template combines Karatsuba and Comba algorithms to control the extra-functional properties of the generated multiplier. The goal is to enable the end user to explore a wide range of possibilities, in terms of performance and resource utilization, without requiring them to know implementation and synthesis details. Experimental results show the large flexibility of the generated architectures and that the generated Pareto-set of multipliers can outperform some state-of-the-art RTL design.

FlexKA: A Flexible Karatsuba Multiplier Hardware Architecture for Variable-Sized Large Integers

“…While there are techniques to unroll the recursion and implement Karatsuba multiplication using HLS, these approaches may not be efficient for all use cases. To solve the reported issue, an approach in literature uses a variadic template to implement the recursion at compile time [12], with a similar Karatsuba-Comba approach as FlexKA. However, in this approach, once the compilation is completed, the multiplier module becomes fixed to the compiled input size.…”

“…There are several hardware implementations of the Karatsuba multiplier, but those designs are often fixed to a specific input operand size [9], [12], [13], [14], [15], [16]. San and At presented a design that supports variable input sizes, but for small operands only [17].…”