Parametric yield optimization for MOS circuit blocks

Hocevar, D.E.; Cox, P.; Yang, Ping

doi:10.1109/43.3204

Cited by 72 publications

(15 citation statements)

References 21 publications

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“…The first challenge is posed by process variation (both inter-die and intra-die) at future technology nodes that will cause defectfree yield to drop sharply. The causes of process variation continue to be the focus of many studies (for example see [1]- [3]) and significant effort is being devoted to innovations in manufacturing and circuit technologies(e.g., adaptive body biasing [4], [5]) to reduce its impact. The second challenge is the continuing divergence of processor and memory speeds.…”

Section: Introductionmentioning

confidence: 99%

Customizable Fault Tolerant Caches for Embedded Processors

Ramaswamy

Yalamanchili

2006

2006 International Conference on Computer Design

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Abstract-The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embedded processors. Concurrently, intra-die and inter-die process variation at future technology nodes will cause defect-free yield to drop sharply unless mitigated. This paper focuses on an architectural technique to configure cache designs to be resilient to memory cell failures brought on by the effects of process variation. Profile-driven re-mapping of memory lines to cache lines is proposed to tolerate failures while minimizing degradation in average memory access time (AMAT) and thereby significantly boosting performance-based die yield beyond that which can be achieved with current techniques. For example, with 50% of the number of cache lines faulty, the performance drop quantified by increase in AMAT using our technique is 12.5% compared to 60% increase in AMAT using existing techniques.

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Section: Introductionmentioning

confidence: 99%

Customizable Fault Tolerant Caches for Embedded Processors

Ramaswamy

Yalamanchili

2006

2006 International Conference on Computer Design

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“…Yield estimation accounts for estimating the expected yield at the current design point (in the multidimensional synthesis case, estimation of the system accuracy) while yield improvement aims at obtaining a new design point with higher yield (higher volume of the perturbation space). In general, yield estimation (see [12] and [13] for an exhaustive review) is carried out either with a Monte Carlo sampling of the parameter space and the associated optimal experiment design methods for reducing the number of samples (response surface methods [13], [16], [17]) or by considering sophisticated boundary methods aimed at generating a description for the yield acceptability frontier (boundary and surface integrals [12], [14], [15]). Subsequent yield improvement techniques move the circuit parameters from an initial configuration toward a new point which maximizes some figure of merit (e.g., the distance from the point to the acceptability region border or its approximation [12]- [15]).…”

Section: Introductionmentioning

confidence: 99%

“…In particular, the optimization method can be applied to any Lebesgue measurable figure of merit (hence, comprising the yield one) without assuming the continuity and/or differentiability hypotheses as required by gradient descent methods [12]- [14] or the memoryless approximating functions assumption requested by surface response techniques methods [13], [16], [17]. In addition, the optimization procedure does not suffer from the presence of local minima in the "yield maximization" figure of merit which is a critical issue in local optimization methods based on gradient estimates.…”

Section: Introductionmentioning

confidence: 99%

An application-level synthesis methodology for multidimensional embedded processing systems

Alippi

Galbusera

Stellini

2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The implementation of multidimensional systems in embedded devices is a major design challenge due to the high algorithmic complexity of the applications. The authors suggest a novel application-level synthesis methodology for those parts of the embedded application which are characterized by being Lebesgue measurable (the computation involved in signal and image processing systems is Lebesgue measurable). The synthesis methodology, based on perturbation analysis, supports the design of analog, digital, or mixed implementations at the very high level of the system design cycle. The outputs of the methodology are quantitative indications regarding the maximum performance loss tolerable by the subsystems composing the application. Such information, augmented with a stochastic description of the tolerated perturbations, can be related to lower synthesis levels and guide the designer toward the final implementation of the embedded device. The perturbation analysis is based on randomized algorithms for an effective evaluation of the performance loss of the computational flow once affected by behavioral perturbations and a Tabu-search-inspired optimizing algorithm for distributing the tolerable performance loss at the system output along the computational subsystems composing the possibly multidimensional processing.

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“…While algorithms for transient sensitivity analysis exist, the computational cost for large circuits with many mismatch variables is still very high. Hocevar, et al [10] used transient sensitivities to estimate yield gradients but limited the number of mismatch parameters to four by modeling the die-to-die variation only.…”

Section: Introductionmentioning

confidence: 99%