Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches

Miller, Timothy N.; Thomas, Renji; Dinan, James; Adcock, Bruce; Teodorescu, Radu

doi:10.1109/micro.2010.28

Cited by 38 publications

(32 citation statements)

References 36 publications

(46 reference statements)

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…We evaluate useful cache capacity, access time and energy consumption of Adapcache and compare to DMR and TMR caches and also to Parichute [3]. We inject random persistent faults according to bit failure rate [0%-12%] by repeating each experiment 100 times.…”

Section: Discussionmentioning

confidence: 99%

“…We calculate the useful cache capacity as the undisabled portion of the cache as can be seen in Figure 2. Bit failure rate for persistent failures in the given Vcc is examined by Miller et al [3] which we reference in our work. Figure 2 presents the Vcc intervals that SCS, DCS and TCS can be used efficiently according to persistent bit failure rate.…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Circuit design of a novel adaptable and reliable L1 data cache

Seyedi

Yalcin

Unsal³

et al. 2013

Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest capacity. Depending on the supply voltage level, Adapcache defines three operating modes: In high supply voltages, Adapcache provides reliability through single-bit parity. In middle range of supply voltages, Adapcache writes data to two separate cache-lines simultaneously in order to use one line for error recovery when the other line is faulty. In near threshold supply voltages, Adapcache writes data to three separate cachelines simultaneously in order to provide the correct data based on bitwise majority voter.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Circuit design of a novel adaptable and reliable L1 data cache

Seyedi

Yalcin

Unsal³

et al. 2013

Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

show abstract

“…Modern processors use various forms of hardware error correction [1,4,8,17,19,21,24]. A large body of research work on novel types of ECC designed to protect vulnerable memory structures exists [2,14,18,26,30,31]. The expected decrease in reliability of future CMOS generations will most likely lead to an increase in ECC coverage on-chip.…”

Section: Related Workmentioning

confidence: 99%

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Bacha

Teodorescu

2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

Self Cite

View full text Add to dashboard Cite

Lowering supply voltage is one of the most effective approaches for improving the energy efficiency of microprocessors. Unfortunately, technology limitations, such as process variability and circuit aging, are forcing microprocessor designers to add larger voltage guardbands to their chips. This makes supply voltage increasingly difficult to scale with technology. This paper presents a new mechanism for dynamically reducing voltage margins while maintaining the chip operating frequency constant. Unlike previous approaches that rely on special hardware to detect and recover from timing violations caused by low-voltage execution, our solution is firmware-based and does not require additional hardware. Instead, it relies on error correction mechanisms already built into modern processors. The system dynamically reduces voltage margins and uses correctable error reports raised by the hardware to identify the lowest, safe operating voltage. The solution adapts to core-to-core variability by tailoring supply voltage to each core's safe operating level. In addition, it exploits variability in workload vulnerability to low voltage execution. The system was prototyped on an HP Integrity Server that uses Intel's Itanium 9560 processors. Evaluation using SPECjbb2005 and SPEC CPU2000 workloads shows core power savings ranging from 18% to 23%, with minimal performance impact.

show abstract

“…Architectures designed specifically to take advantage of low voltage properties such as fast caches relative to logic have been proposed by Zhai et al [39] and Dreslinski et al [9]. Other work has focused on improving the reliability of large caches in low voltage processors [11,29]. While significant progress has been made in bringing this technology to market, including a prototype processor from Intel [38], many challenges remain, including reliability and high variation.…”

Section: Low Voltage Designsmentioning

confidence: 99%

“…A very effective approach to improving the energy efficiency of a microprocessor is to lower its supply voltage (V dd ) to very close to the transistor's threshold voltage (V th ), into the so-called near-threshold (NT) region [5,8,26,29]. This is significantly lower than what is used in standard dynamic voltage and frequency scaling (DVFS), resulting in aggressive reductions in power consumption (up to 100×) with about a 10× loss in maximum frequency.…”

Section: Introductionmentioning

confidence: 99%

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Miller

Pan

Thomas

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

Self Cite

View full text Add to dashboard Cite

Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process variation, which can lead to large differences in the maximum frequency achieved by individual cores. This paper presents Booster, a simple, low-overhead framework for dynamically rebalancing performance heterogeneity caused by process variation and application imbalance. The Booster CMP includes two power supply rails set at two very low but different voltages. Each core can be dynamically assigned to either of the two rails using a gating circuit. This allows cores to quickly switch between two different frequencies. An on-chip governor controls the timing of the switching and the time spent on each rail. The governor manages a "boost budget" that dictates how many cores can be sped up (depending on the power constraints) at any given time. We present two implementations of Booster: Booster VAR, which virtually eliminates the effects of core-to-core frequency variation in near-threshold CMPs, and Booster SYNC, which additionally reduces the effects of imbalance in multithreaded applications. Evaluation using PARSEC and SPLASH2 benchmarks running on a simulated 32-core system shows an average performance improvement of 11% for Booster VAR and 23% for Booster SYNC.

show abstract

Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches

Abstract: Energy efficiency is a primary concern for microprocessor designers

Cited by 38 publications

References 36 publications

Circuit design of a novel adaptable and reliable L1 data cache

Circuit design of a novel adaptable and reliable L1 data cache

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

Contact Info

Product

Resources

About