Parlgran: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

Banerjee,; Bozorgzadeh,; Dutt, Nikil

doi:10.1109/aspdac.2006.1594733

Cited by 10 publications

(21 citation statements)

References 11 publications

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“…Good speedups over the DSP processor are shown (between 3 and 20 times). Molen [59], ROCCC [54], DRESC [55], PARLGRAN [56] and the approaches presented in [57,58] are representative examples that exploit the parallelism of loops by using techniques such as loop unrolling and software pipelining to boost the performance of applications.…”

Section: Traditional Reconfigurable Systems and Hls Synthesismentioning

confidence: 99%

A transparent and adaptive reconfigurable system

Beck

Rutzig

Carro

2014

Microprocessors and Microsystems

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Section: Traditional Reconfigurable Systems and Hls Synthesismentioning

confidence: 99%

A transparent and adaptive reconfigurable system

Beck

Rutzig

Carro

2014

Microprocessors and Microsystems

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“…Previous work [2] has also attempted to exploit data-parallelism with partial RTR with suitable task workload selection -however, their principles are not applicable when bandwidth is limited.…”

Section: Introductionmentioning

confidence: 98%

Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures

Banerjee

Bozorgzadeh

Noguera

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources such as data bandwidth, configurable logic, and the limited logic resources are customized during application execution with partial RTR. In this work, we present key theoretical principles for maximizing application performance when available bandwidth is limited. We exploit bandwidth very effectively by selecting a suitable clock frequency for each task and maximize performance with partial RTR by exploiting data-parallelism property of common image-processing tasks. Our theoretical principles are integrated in our scheduling strategy, SCHEDRTR. We present detailed application case studies on a cycle-accurate simulation platform that addresses microarchitectural concerns and includes detailed resource considerations of the Virtex XC2V3000 device. Our results demonstrate that applying SCHEDRTR to common image-filtering applications leads to 15-20% performance gain in scenarios with limited bandwidth, when compared to a sophisticated RTR scheduling strategy with data-parallelism but simpler bandwidth considerations.

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“…The goal in [13] is to define a specific methodology for scheduling the tasks of these applications in order to reduce the overall completion time. The same authors present in [7] an enhanced solution for the same problem: PARLGRAN tries to reduce the total execution time using two different techniques. The former one is called simple fragmentation reduction and it places the new task in the first available area on the FPGA in the opposite side of the FPGA with respect to the location of the previous task.…”

Section: Related Workmentioning

confidence: 99%

“…Module reuse means that two tasks of the same type have the possibility to be executed exactly on the same module on board, hiding completely the reconfiguration time. Configuration prefetching and module reuse are combined with time partitioning techniques to optimize the latency of the application [7] [8] [9]. Anti-fragmentation techniques avoid the fragmentation of the available space on board trying to maximize the dimension of free adjacent areas.…”

Section: Introductionmentioning

confidence: 99%

Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems

Redaelli¹,

Santambrogio²,

Sciuto³

2008

2008 Design, Automation and Test in Europe

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Aim of this paper is to define a scheduling of the task graph of an application that minimizes its total execution time on a partially dynamically reconfigurable FPGA. The scheduler has to take into account the reconfiguration overhead of each task, the area constraint of the target FPGA, the precedences between the tasks, configuration prefetching and module reuse. We introduce an ILP formulation to solve the task scheduling problem in the reconfigurable architecture scenario. This formulation has been used to identify interesting features for a possible heuristic scheduler. The results of the ILP solution show how a reconfiguration-aware scheduler exploiting all the reconfiguration features can outperform one with partial knowledge.

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Parlgran: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

Cited by 10 publications

References 11 publications

A transparent and adaptive reconfigurable system

A transparent and adaptive reconfigurable system

Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures

Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems

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